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參數資料
型號: 7872
廠商: Maxwell Technologies, Inc
英文描述: Enclosed Switches Series LS: Side Rotary with 1.5" Fixed Length Lever; Steel Roller; 1NC 1NO DPDT Snap Action, Double Break; 0.5 in - 14NPT conduit; Plug-in
中文描述: 14位A / D轉換器
文件頁數: 5/11頁
文件大小: 154K
代理商: 7872
M
5
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
14-Bit A/D Converter
7872
5.21.02 Rev 4
T
ABLE
10. 7872 DC E
LECTRICAL
C
HARACTERISTICS
FOR
P
OWER
R
EQUIREMENTS
(V
DD
= 5V ±5%, V
SS
= -5 V ± 5%, T
A
= -55
TO
125 °C
UNLESS
OTHERWISE
SPECIFIED
)
S
YMBOL
C
ONDITIONS
P
ARAMETER
R
EQUIREMENTS
U
NITS
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
Power Dissipation
V
DD
V
SS
I
DD
I
SS
P
D
5% for Specified Performance
5% for Specified Performance
Typically 6mA
Typically 4mA
Typically 50mW
5
-5
13
6
95
V
V
mA max
mA max
mW max
T
ABLE
11. 7872 T
IMING
C
HARACTERISTICS
1,2
(V
DD
= 5V ±5%, V
SS
= -5 V ± 5%, T
A
= -55
TO
125 °C
UNLESS
OTHERWISE
SPECIFIED
)
1. All input signals are specified with tr = tr = 5 ns (10% to 90% of 5 V) and timed froma voltage level of 1.6 V.
2. Serial timng is measured with a 4.7 k
pull-up resistor on SDATA and SSTRB and a 2 k
pull-up resistor on SCLK. The
capacitance on all three outputs is 35 pF.
3. SCLK mark/space ration (measured froma voltage level of 1.6 V) is 40/60 to 60/40.
4. SDATA will drive higher capacitive loads, but this will add to t
12
since it increases the external RC time constant (4.7k
/C
L
) and
hence, the time to reach 2.4 V.
P
ARAMETER
/C
ONDITION
S
YMBOL
S
UBGROUPS
M
IN
M
AX
U
NITS
CONVST Pulse Width
t
1
t
10
t
11
t
12
t
13
t
14
9, 10, 11
50
--
ns
SSTRB to SCLK Falling Edge Setup Time
9, 10, 11
100
--
ns
SCLK Cycle Time
3
9, 10, 11
440
--
ns
SCLK to Valid Data Delay: C
L
= 35 pF
4
SCLD Rising Edge to SSTRB
9, 10, 11
--
155
ns
9, 10, 11
20
150
ns
Bus Relinquish Time After SCLK
9, 10, 11
4
100
ns
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