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參數(shù)資料
| 型號(hào)： | 78M6613-IMR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, QFN-32 |
| 文件頁數(shù)： | 30/33頁 |
| 文件大小： | 957K |
| 代理商： | 78M6613-IMR/F |
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78M6613 Data Sheet
DS_6613_018
6
Rev. 1.1
1.2
Analog Front End (AFE)
The AFE of the 78M6613 is comprised of an input multiplexer, a delta-sigma A/D converter and a
voltage reference.
1.2.1
Input Multiplexer
The input multiplexer supports up to four input signals that are applied to pins A0, A1, A2 and A3 of the
device. Additionally, using the alternate mux selection, it has the ability to select the on-chip
temperature sensor. The multiplexer can be operated in two modes:
During a normal multiplexer cycle, the signals from the A0, A2, A1, and A3 pins are selected.
During the alternate multiplexer cycle, the temperature signal (TEMP) is selected, along with the
signal sources shown in Table 1.
The alternate mux cycles are usually performed infrequently (e.g. every second) by the MPU. Table 1
details the regular and alternative MUX sequences. Missing samples due to an ALT multiplexer
sequence are filled in by the CE.
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
Regular MUX Sequence
ALT MUX Sequence
Mux State
0
1
2
3
0
1
2
3
A0
A1
A2
A3
TEMP
A1
V3P3D
A3
In a typical application, A1 and A3 are connected to current sensors that sense the current on each
branch of the line voltage. A0 and A2 are typically connected to voltage sensors through resistor
dividers. The multiplexer control circuit is clocked by CK32, the 32.768 kHz clock from the PLL block,
and launches with each new pass of the CE program.
1.2.2
A/D Converter (ADC)
A single delta-sigma A/D converter digitizes the voltage and current inputs to the 78M6613. The
resolution of the ADC is 22 bits. Conversion time is two cycles of the CK32 clock.
Initiation of each ADC conversion is controlled by the multiplexer control circuit as described previously.
At the end of each ADC conversion, the FIR filter output data is stored into the CE DRAM location.
1.2.3
FIR Filter
The finite impulse response filter is an integral part of the ADC and it is optimized for use with the
multiplexer. The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the
end of each ADC conversion, the output data is stored into the fixed CE DRAM location determined by
the multiplexer selection.
1.2.4
Voltage References
The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero
techniques. The reference is trimmed to minimize errors caused by component mismatch and drift. The
result is a voltage output with a predictable temperature coefficient.
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