- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369350 > 78P2253-IGT (Electronic Theatre Controls, Inc.) XTAL CER SMT 11X5 4PAD PDF資料下載
參數(shù)資料
| 型號： | 78P2253-IGT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XTAL CER SMT 11X5 4PAD |
| 中文描述： | 收發(fā)器 |
| 文件頁數(shù)： | 3/23頁 |
| 文件大小： | 107K |
| 代理商： | 78P2253-IGT |
78P2253
E4/STM-1/STS-3/OC-3
Transceiver
3
TRANSMITTER OPERATION
(continued)
XTAL1
XTAL2
CKIN
FIGURE 1A:
USING CRYSTAL
XTAL1
XTAL2
CKIN
17.283 MHz (E4)
19.440 MHz (Sonet)
FIGURE 1B:
USING EXTERNAL CLOCK
In ECL mode the data signal is converted to CMI
code by the Binary to CMI encoded.
The HUB/
HOST
input changes the reference signal
for the clock generator. In the hub mode (HUB/
HOST
high), the transmit clock reference is derived from
either the crystal oscillator or CKIN. In host mode
(HUB/
HOST
low), the transmit clock reference is
derived from the recovered receive clock.
RECEIVER OPERATION
The receiver accepts serial, CMI coded data, at
155.52Mbit/s or 139.264Mbit/s from either the CMI
or the ECL inputs. In CMI mode, the inputs CMIINP
and CMIINN receive the input signal from a coaxial
cable that is transformer-coupled to the chip. The
ECL pins should be left open. In ECL mode, the pins
ECLINP and ECLINN receive the input signal.
In CMI mode, the received signal is equalized for
dispersive cable attenuation and decoded in the CMI
to binary decoder.
A clock signal is recovered using a low jitter PLL
circuit.
The data is converted to binary by the CMI to Binary
decoder.
In serial mode, the received data is output on the
RXDTP and RXDTN pins and the recovered clock is
output on the RXCKP and RXCKN pins.
In parallel mode, the received data is converted to
parallel, eight bits if 8BIT/
$BIT
is high and four if it is
low. The first bit received will arrive on the most
significant output pin, RXDT[7] in eight bit mode and
RXDT3 in four bit mode.
The LOS pin goes high when the signal detector
detects a loss-of-signal condition.
LOOPBACK OPERATION
The 78P2253 is capable of performing signal
loopback in two ways The RLBACK pin selects the
remote loopback mode. In this mode, the received
signal is “l(fā)ooped back” and sent out of transmitter in
place of the transmit input signal.
The LLBACK pin selects the local loop-back mode,
and causes the receiver to use the transmitter output
signal as its input. Local loopback is disabled when
HUB/
HOST
is low or RLBACK is high.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 78P7200 | Line Interface Unit |
| 78P7200-IH | Line Interface Unit |
| 78P7200 | E3/DS3/STS-1 Transceiver |
| 78P7200L | E3/DS3/STS-1 Transceiver |
| 78P7200L-IGT | E3/DS3/STS-1 Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 78P2254 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:OC-3 / STM-1 / STS-3 / E4 Transceivers |
| 78P2254-IGT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| 78P2342-IGT | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:2-port E3/DS3/STS-1 LIU with Jitter Attenuator |
| 78P2342-IGT/A07 | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:2-port E3/DS3/STS-1 LIU with Jitter Attenuator |
| 78P2342-IGT/F | 制造商:Maxim Integrated Products 功能描述:LEAD FREE - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。