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參數(shù)資料
| 型號： | 78P7200-IH |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Line Interface Unit |
| 中文描述： | 線路接口單元 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 171K |
| 代理商： | 78P7200-IH |
78P7200
E3/DS3/STS-1
Line Interface Unit
EXTERNAL COMPONENTS
(Dependent on speed, nominal Value)
Page: 7 of 11
2005 Teridian Semiconductor Corporation
Rev 3.0
STS-1
DS3
E3
Loop center frequency resistor RFO
1% tolerance
4.53
5.23
6.81
k
pF
Transmit termination capacitor CTT
Transmit termination resistor
5% (Note 2)
1%
10
301
10
301
3
RTT
604
Note 1: Optional capacitor to reduce common mode noise.
Note 2: C
TT
value depends on the PC board design. Nominal values are selected for 78P7200 Demo Board.
DIGITAL INPUTS AND OUTPUTS
(CMOS-compatible pins:
LOWSIG
, RPOS, RNEG, RCLK, TPOS, TNEG, TCLK, LBO,
OPT!
.) Currents flowing
into the chip are positive. Current maximums are currents with the largest absolute value.
PARAMETER
Input low voltage
Input high voltage
CONDITIONS
MIN
-0.3
3.5
NOM
MAX
1.5
Vcc
+0.3
5
5
0.4
UNIT
V
V
VIL
VIH
Input low current
Input high current
Output low voltage
Output high voltage
IIL
IIH
VOL
VOH
VIL = 1.5V
VIH = 3.5V
IOL = 0.1 mA
IOH = -0.1 mA
-5
-5
4
μA
μA
V
V
CHARACTERISTICS
OPT@
Input low voltage
Input high voltage
RECEIVER
All of the measurements for the receiver are made with the following conditions unless otherwise stated:
1. The input signal is transformer coupled as shown in Figure 1.
2. RFO = 5.23 k
for DS3, 6.81 k
for E3 and 4.53 k
for STS-1.
VIL
VIH
IIL = 0.4 mA
0.5
V
V
2
Input AC-Coupled
CPD = 0.022 μF
CPD not used
±0.045
±0.090
15
±1.2
±1.2
30
V
V
k
Input signal voltage
Short cable (3’)
VIN
Input Resistance
RIN
Input at device's common mode
voltage
Relative to peak amplitude for
22.37/17.18/25.92 MHz
sinusoidal input
20
Receive data detection
threshold
VDTH
50
%
Receive data low signal
threshold
Receive data low signal
delay
VLOW
±20
±50
mV
CPD = 0.022 μF
CPD not used
VIN(max) = ±250 mV
500
μs
μs
TLOW
0.5
3
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