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參數(shù)資料
| 型號(hào)： | 78P7200L-IGT |
| 廠商： | TDK Corporation |
| 英文描述： | E3/DS3/STS-1 Transceiver |
| 中文描述： | E3/DS3/STS-1收發(fā)器 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大小： | 171K |
| 代理商： | 78P7200L-IGT |
78P7200
E3/DS3/STS-1
Line Interface Unit
ELECTRICAL SPECIFICATIONS
(TA = -40°C to 85°C, Vcc = 5V ±5%, unless otherwise noted.) Currents flowing into the chip are positive. Current
maximums are currents with the largest absolute value. Operation above absolute maximum ratings may
permanently damage the device.
ABSOLUTE MAXIMUM RATINGS
Page: 6 of 11
2005 Teridian Semiconductor Corporation
Rev 3.0
PARAMETER
Positive 5V supply: TVcc, RVcc, DVcc
Storage Temperature
Soldering Temperature (10 sec.)
Ambient Operating Temperature, TA
Pin Ratings: LOUT+, LOUT-
LIN+, LIN-, TPOS, TNEG, TCLK, LBO, RFO, LF2, LF1,
OPT!
,
OPT@
Pins
RPOS, RNEG, RCLK, LOWSIG Pins
SUPPLY CURRENTS AND POWER
RATING
6V
-65 to 150°C
260 °C
-40 to +85°C
Vcc -2 to Vcc +2V
-0.3 to Vcc +0.3V
-0.3 to Vcc +0.3V or +12 mA
PARAMETER
Supply Current
CONDITIONS
Outputs unloaded, normal
operation, transmit and receive
all 1's pattern
Outputs unloaded, TA = 85°C
MIN
NOM
155
MAX
190
UNIT
mA
ICC
Power Dissipation
EXTERNAL COMPONENTS
(Common to STS-1/DS3/E3, nominal value)
P
0.93
W
Loop filter resistor
RLF1
1% tolerance
6.04
k
k
μF
μF
pF
pF
μF
μH
μH
Loop filter resistor
RLF2
1%
100
Loop filter capacitor
Peak detector capacitor
Input Filter
CLF1
CPD
R1, R2
5%
10%
1%
0.22
0.022
75
Input Filter
Input Filter
Input Filter
Input Filter
Input Filter
Transformer Turns Ratio
Receiver Termination ResistorRTR
C1
C2
C3
L1
L2
5%
5%
20% (See Note)
5%
5%
3%
1%
1000
82
0.47
6.8
1:2
422
0.01
T1, T2
Note: Optional capacitor to reduce common mode noise.
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