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參數(shù)資料
型號(hào)： 79RC32T355-180DHI
廠商： Integrated Device Technology, Inc.
英文描述： IDT Interprise Integrated Communications Processor
中文描述： IDT的洽談會(huì)集成通信處理器
文件頁(yè)數(shù)： 1/47頁(yè)
文件大小： 987K
代理商： 79RC32T355-180DHI
1 of 47
May 25, 2004
2004 Integrated Device Technology, Inc.
DSC 5900
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Features List
◆
RC32300 32-bit Microprocessor
–
Enhanced MIPS-II ISA
–
Enhanced MIPS-IV cache prefetch instruction
–
DSP Instructions
–
MMU with 16-entry TLB
–
8KB Instruction Cache, 2-way set associative
–
2KB Data Cache, 2-way set associative
–
Per line cache locking
–
Write-through and write-back cache management
–
Debug interface through the EJTAG port
–
Big or Little endian support
◆
Interrupt Controller
–
Allows status of each interrupt to be read and masked
◆
I
2
C
–
Flexible I
2
C standard serial interface to connect to a variety of
peripherals
–
Standard and fast mode timing support
–
Configurable 7 or 10-bit addressable slave
◆
UARTs
–
Two 16550 Compatible UARTs
–
Baud rate support up to 1.5 Mb/s
◆
Counter/Timers
–
Three general purpose 32-bit counter/timers
◆
General Purpose I/O Pins (GPIOP)
–
36 individually programmable pins
–
Each pin programmable as input, output, or alternate function
–
Input can be an interrupt or NMI source
–
Input can also be active high or active low
◆
SDRAM Controller
–
2 memory banks, non-interleaved, 512 MB total
–
32-bit wide data path
–
Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips
–
SODIMM support
–
Stays on page between transfers
–
Automatic refresh generation
◆
Peripheral Device Controller
–
26-bit address bus
–
32-bit data bus with variable width support of 8-,16-, or 32-bits
–
8-bit boot ROM support
–
6 banks available, up to 64MB per bank
–
Supports Flash ROM, PROM, SRAM, dual-port memory, and
peripheral devices
–
Supports external wait-state generation, Intel or Motorola style
–
Write protect capability
–
Direct control of optional external data transceivers
◆
System Integrity
–
Programmable system watchdog timer resets system on time-
out
–
Programmable bus transaction times memory and peripheral
transactions and generates a warm reset on time-out
◆
DMA
–
16 DMA channels
–
Services on-chip and external peripherals
–
Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O
transfers
–
Supports flexible descriptor based operation and chaining via
linked lists of records (scatter / gather capability)
–
Supports unaligned transfers
–
Supports burst transfers
Block Diagram
Figure 1 RC32355 Internal Block Diagram
EJTAG
MMU
D. Cache
I. Cache
RC32300
CPU Core
ICE
Interrupt
Controller
3 Counter
Timers
Watchdog
Timer
10/100
Ethernet
Interface
USB
Interface
16 Channel
DMA
Controller
Arbiter
Ext. Bus
Master
SDRAM &
Device
Controller
2 UARTS
(16550)
GPIO
Interface
ATM
Interface
Memory &
Peripheral Bus
Ch. 1 Ch. 2
Serial Channels
GPIO Pins
Utopia 1 / 2
Interface
Controller
TDM
I
2
C
TDM Bus
I
2
C Bus
:
:
79RC32355
IDT
TM
Interprise
TM
Integrated
Communications Processor
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