
Philips Semiconductors Microcontroller Products
Application Note
AN408
80C451 operation of port 6
1
March 1988
INTRODUCTION
The features of the 80C451 are shared with
the 80C51 or are conventional except for the
operation of port 6. The flexibility of this port
facilitates high-speed parallel data
communications. This application note
discusses the use of port 6 and is divided into
the following sections:
1. Port 6 as a processor bus interface.
2. Using port 6 as a standard pseudo
bidirectional I/O port.
3. Implementation of parallel printer ports.
This information applies to all versions of the
part: 80C451, 83C451, and the 87C451.
PORT 6 AS A PROCESSOR BUS
INTERFACE
Port 6 allows use of the 80C451 as an
element on a microprocessor type bus. The
host processor could be a general purpose
MPU or the data bus of a microcontroller like
the 80C451 itself. This feature allows single
or multiple 80C451 controllers to be used on
a bus as flexible peripheral processing
elements. Applications could include
keyboard scanners, serial I/O controllers,
servo controllers, etc.
OPERATION
On reset, port 6 is programmed correctly for
use as a bus interface (see 2). This prevents
the interface from disrupting data on the bus
of the host processor during power-up.
Software initialization of the CSR (Control
Status Register) is not required. A dummy
read of port 6 may be required to clear the
IBF (Input Buffer Full) flag since it could be
set by turn on transients on the bus of the
host processor. On reset, the CSR of the
83C451 is programmed to allow the following:
1. AFLAG is an input controlling the port
select function. If AFLAG is high, the
contents of the CSR is output on port 6
when the port is read by the host. If
AFLAG is low, then the contents of the
output latch is output when port 6 is read
by the host.
2. BFLAG is an input controlling the port
enable function. In this mode when
BFLAG is high, the input latch and the
output drivers are disabled and the flags
are not affected by the IDS (Input Data
Strobe) or ODS (Output Data Strobe)
signals. When BFLAG is low, the port is
enabled for reading and writing under the
control of IDS and ODS pins.
Figure 1 shows one possible example of an
80C451 on a memory bus. This arrangement
allows the main processor to query port 6 for
flag status without interrupting the 80C451. If
the address decoder, shown in Figure 1,
enables port 6 on the 80C451 when the
address is 8000H or 8001H, and the address
line A0 controls the port select feature, then
the host processor can read and write to port
6 using address 8000H. Since the port select
function is being controlled by the address
line A0, the CSR contents can be read by the
host processor at address 8001H.
By testing the CSR contents in this way, the
host processor can tell if new data has been
written to the port 6 output latch since it last
read the port or if the 80C451 has read the
last byte that the host wrote to the port.
Conversely, the 80C451 can poll the flags in
its CSR to see if the host processor has
written to or read from port 6 since the last
time it serviced the port.
If desired, an interrupt source for the 80C451
can be derived easily from the port enable
source as shown by the dashed line in
Figure 1.
8
Host
Processor
80C451
82S163
Address
Decoder
74HCT373
Latch
6116
Static RAM
Address
SEL
(AFLAG)
IDS ODS P6
WR
RD
D0-D7
CE
RD
WR
AD0-AD7
ALE
A8-An
LE
A0
SU00332
Figure 1. An 83C451 on a Microprocessor Memory Bus