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參數資料
| 型號： | 8213AM |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數： | 1/33頁 |
| 文件大小： | 171K |
| 代理商： | 8213AM |
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SM8213AM
NIPPON PRECISION CIRCUITS—1
NIPPON PRECISION CIRCUITS INC.
POCSAG Decoder For Multiframe Pagers
OVERVIEW
The SM8213AM is a POCSAG-standard (Post
Office Code Standardization Advisory Group) signal
processor LSI, which conforms to CCIR recommen-
dation 584 concerning standard international wire-
less calling codes.
The SM8213AM supports call messages in either
tone, numerical or character outputs at signal speeds
of 512, 1200 or 2400 bps. The signal input stage fea-
tures a built-in filter.
Each of the addresses (max. 7 + 1 dummy = 8) can
be assigned to any frame, which also makes the
device configurable for many additional services.
Each address can be independently set to ON/OFF.
Furthermore, built-in buffer memory means decoded
information can be fetched in sync with the micro-
controller clock, thereby reducing the microcontrol-
ler CPU time required. Intermittent-duty method
(battery saving (BS) method) control signals, com-
patible with PLL operation, and Molybdenum-gate
CMOS structure makes possible the construction of
low-voltage operation, low power dissipation sys-
tems.
The SM8213AM is available in 16-pin SSOPs.
FEATURES
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Conforms to POCSAG standard for pagers
512, 1200 or 2400 bps signal speed
Multiframe compatible (each address individually
controllable)
8 addresses
×
4 sub-addresses (total of 32
addresses) control
(8 addresses comprise 7 actual addresses + 1
dummy address)
Built-in buffer memory (1 code word)
Supports tone, numeric or character call messages
Built-in input signal filter, with filter ON/OFF and
4 selectable filter characteristics
PLL-compatible battery saving method (BS1,
BS2, BS3 outputs)
BS1 (RF control main output signal) 61-step setup
time setting
BS3 (PLL setup signal) 61-step setup time setting
BS2 (RF DC-level adjustment signal) before/dur-
ing reception selectable adjustment timing
1-bit and 2-bit burst error auto-correction function
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25 to 75% duty factor signal coverage
8 rate error detection condition settings
76.8 kHz system clock (crystal oscillator)
76.8 or 38.4 kHz clock output pin
Built-in oscillator capacitor and feedback resistor
2.0 to 3.5 V operating supply voltage
Molybdenum-gate CMOS process realizes low
power dissipation
16-pin SSOP
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PINOUT
Top View
PACKAGE DIMENSIONS
Unit: mm
ATTN
SDI
SDO
SCK
AREA
RSTN
BS1
BS2
BS3
VDD
XVSS
XT
XTN
VSS
CLKO
SIGNAL
8
1
8
9
16
0.6TYP
6.8 0.3
0.8
0.36 0.1
0.4 0.2
0 10
0.15
- 0.05
0
1
4
6
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