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參數(shù)資料
| 型號： | 87021AMIT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 87021 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 3.90 X 4.90 MM, 1.37 MM HEIGHT, MS-012, SOIC-8 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 290K |
| 代理商： | 87021AMIT |
÷1/÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL
CLOCK GENERATOR
ICS87021I
IDT / ICS LVCMOS CLOCK GENERATOR
1
ICS87021AMI REV. B AUGUST 26, 2008
GENERAL DESCRIPTION
The ICS87021I is a high perfor mance ÷1/÷2
Differential-to-LVCMOS/LVTTL Clock Generator
and a member of the HiPerClockS family of High
Performance Clock Solutions from IDT. The CLK,
nCLK pair can accept most standard differential
input levels. Guaranteed part-to-part skew characteristics make
the ICS87021I ideal for those clock distribution applications de-
manding well defined performance and repeatability.
FEATURES
Two single-ended LVCMOS/LVTTL outputs
One differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 250MHz
Additive phase jitter, RMS: 0.18ps (typical)
Output skew: 50ps (maximum)
Part-to-part skew: 450ps (maximum)
Propagation delay: 3.4ns (maximum)
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
Availalbe in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
HiPerClockS
ICS
ICS87021I
8-Lead SOIC
3.90mm x 4.90mm x 1.375mm package body
M Package
Top View
CLK
nCLK
MR
F_SEL
1
2
3
4
VDD
Q0
Q1
GND
8
7
6
5
Q0
Q1
CLK
nCLK
MR
F_SEL
0
1
÷1
÷2
R
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