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參數資料
| 型號： | 8741004AGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 8741004 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 4 40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 |
| 文件頁數： | 1/19頁 |
| 文件大小： | 784K |
| 代理商： | 8741004AGLF |
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL
PCI EXPRESS JITTER ATTENUATOR
ICS8741004
IDT / ICS PCI EXPRESS JITTER ATTENUATOR
1
ICS8741004AG REV. AMAY 29, 2008
General Description
The ICS8741004 is a high performance
Differential-to-LVDS/0.7V Differential Jitter
Attenuator designed for use in PCI Express
systems. In some PCI Express systems, such as
those found in desktop PCs, the PCI Express clocks
are generated from a low bandwidth, high phase noise PLL
frequency synthesizer. In these systems, a jitter attenuator may be
required to attenuate high frequency random and deterministic
jitter components from the PLL synthesizer and from the system
board. The ICS8741004 has 3 PLL bandwidth modes: 200kHz,
600kHz and 2MHz. The 200kHz mode will provide maximum jitter
attenuation, but with higher PLL tracking skew and spread
spectrum modulation from the motherboard synthesizer may be
attenuated. The 600kHz provides an intermediate bandwidth that
can easily track triangular spread profiles, while providing good
jitter attenuation. The 2MHz bandwidth provides the best tracking
skew and will pass most spread profiles, but the jitter attenuation
will not be as good as the lower bandwidth modes. Because some
2.5Gb serdes have x20 multipliers while others have x25
multipliers, the ICS8741004 can be set for 1:1 mode or 5/4
multiplication mode (i.e. 100MHz input/125MHz output) using the
F_SEL pins.
The ICS8741004 uses IDT’s 3rd Generation FemtoClock
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making it
ideal for use in space constrained applications such as PCI
Express add-in cards.
PLL Bandwidth
Features
Two LVDS and two 0.7V differential output pairs
Bank A has two LVDS output pairs and
Bank B has two 0.7V differential output pairs
One differential clock input pair
CLK, CLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 160MHz
Input frequency range: 98MHz - 128MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 35ps (maximum)
Full 3.3V operating supply
Three bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
ICS8741004
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~600kHz (default)
1 = PLL Bandwidth: ~2MHz
HiPerClockS
ICS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQA1
QA1
VDDO
QA0
nQA0
MR
BW_SEL
nc
VDDA
F_SELA
VDD
OEA
nQB1
QB1
VDDO
QB0
nQB0
IREF
F_SELB
OEB
GND
nCLK
CLK
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 8741004AGLFT | 功能描述:時鐘合成器/抖動清除器 LVDS/HCSL PCIe Jitter Attenuator RoHS:否 制造商:IDT 輸出端數量:2 輸出電平:LVCMOS, LVDS, LVPECL 最大輸出頻率:250 MHz 輸入電平:HCSL, LVDS, LVHSTL, LVPECL 最大輸入頻率:710 MHz 電源電壓-最大:3.465 V 電源電壓-最小:3.135 V 封裝 / 箱體:VFQFN-40 封裝: |
| 8741004AGT | 制造商:Integrated Device Technology Inc 功能描述:PLL FREQ SYNTHESIZER SGL 24TSSOP - Tape and Reel |
| 8741004BGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS⑩ JITTER ATTENUATOR |
| 8741004BGILF | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 8741004BGILFT | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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