
T
S
PRODUCT OVERVIEW
The Marvell
transceivers. The 88X2010 transceiver provides dedicated 10 GbE and 10 Gigabit Fibre Channel (GFC) LAN PHY
serial operation. The 88X2011 device incorporates WAN Interface Sublayer (WIS) functionality and can be used
for LAN and WAN PHY applications. WIS functionality enables the transmission of Ethernet data over SONET
networks. These transceivers perform all of the necessary serial 10 Gbps to XAUI conversion functions, while
achieving a very low power dissipation of 1.4 Watts. The parallel and serial interfaces on the device are IEEE
802.3ae 10 Gigabit Attachment Unit Interface (XAUI) and PMA serial interface (XFI compliant), respectively.
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Alaska
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X devices (88X2010 and 88X2011) are CMOS 10 Gigabit Ethernet (GbE) serial interface
The Alaska X devices incorporate serial 10 Gbps and XAUI Serializer/Deserializer (SERDES) with on-chip clock
generation and recovery. In addition, the devices feature IEEE 802.3ae compliant PCS, PMA, WIS, and XGXS
functionality. Both the 88X2010 and 88X2011 devices support industry standard management interface through
their MDIO ports. The devices small form factor and low power consumption make them ideal for XENPAK, XPAK
and X2 fiber optic modules. The 88X2010 and 88X2011 devices are also suitable for XFP module-based applications.
Fig 1. Alaska X 10 Gigabit Transceiver (88W2010/88X2011) Block Diagram
Alaska
X
10 Gigabit Ethernet and 10 Gigabit
Fibre Channel LAN/WAN Transceivers
88X2010/88X2011
TBG/Clock
Synthesizer
Clock and
Data
Recovery
Management
Interface
NVR
Registers
LASI
LEDs
JTAG
L3_RXP/N
L2_RXP/N
L1_RXP/N
L0_RXP/N
L3_TXP/N
L2_TXP/N
L1_TXP/N
L0_TXP/N
S_IN
S_IP
S_CN
S_CP
S_ON
S_OP
INTn
MDIO
MDC
TDO
TMS
TDI
TCK
TRSTn
X
S
8B/10B
Decoder
64B/66B
Encoder
Serializer
8B/10B
Encoder
FIFO
FIFO
64B/66B
Decoder
Deserializer
WIS
(88X2011)
FEATURES
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Selectable WAN interface sublayer (88X2011)
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IEEE 802.3ae XAUI parallel interface
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XFI compliant serial 10 G interface
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10.3125 to 10.51875 Gbps data rates (LAN PHY)
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9.953 Gbps data rate (WAN PHY88X2011 only)
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On-chip clock generation and clock recovery
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On-chip 64B/66B encoder/decoder
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Internal CJPAT, CRPAT and PRBS test pattern generators
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Low power dissipation: 1.4 Watts
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IEEE 802.3ae MDIO interface
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IEEE 1149.1 JTAG test interface
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Small 256-pin TFBGA package (17mm x 17mm)
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0.13-micron CMOS process
BENEFITS
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WAN or LAN configurable operation
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IEEE compliant interface ensures interoperability
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Serial 10 G module MSA interoperability
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Supports 10 GbE and 10 GFC
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Supports SONET and SDH transmission
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Simplifies system timing requirements
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Provides standards compliant coding
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Assists in testing and diagnostics
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Lowers overall system power
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Eases programmability
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Allows for superior manufacturability
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Occupies less board space
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State-of-the-art production process