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參數資料
| 型號： | 9084901MCA |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 |
| 封裝： | HERMETIC SEALED, CERAMIC, DIP-14 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 458K |
| 代理商： | 9084901MCA |
1
Data sheet acquired from Harris Semiconductor
SCHS139D
Features
Hysteresis on Clock Inputs for Improved Noise Immu-
nity and Increased Input Rise and Fall Times
Asynchronous Reset
Complementary Outputs
Buffered Inputs
Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
TA = 25
oC
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55oC to 125oC
Balanced Propagation Delay and Transition Times
Signicant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1A at VOL, VOH
Description
The ’HC107 and CD74HCT107 utilize silicon gate CMOS
technology to achieve operating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads.
These ip-ops have independent J, K, Reset and Clock
inputs and Q and Q outputs. They change state on the
negative-going transition of the clock pulse. Reset is
accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT73 but
differs in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible
with the standard LS family.
Pinout
CD54HC107 (CERDIP)
CD74HC107 (PDIP, SOIC)
CD74HCT107 (PDIP)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC107F3A
-55 to 125
14 Ld CERDIP
CD74HC107E
-55 to 125
14 Ld PDIP
CD74HC107M
-55 to 125
14 Ld SOIC
CD74HC107MT
-55 to 125
14 Ld SOIC
CD74HC107M96
-55 to 125
14 Ld SOIC
CD74HCT107E
-55 to 125
14 Ld PDIP
NOTE: When ordering, use the entire part number. The sufx 96
denotes tape and reel. The sufx T denotes a small-quantity reel of
250.
1J
1Q
1K
2Q
GND
VCC
1R
1CP
2K
2R
2CP
2J
1
2
3
4
5
6
7
14
13
12
11
10
9
8
March 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC107, CD74HC107,
CD74HCT107
Dual J-K Flip-Flop with Reset
Negative-Edge Trigger
[ /Title
(CD74
HC107
,
CD74
HCT10
7)
/Sub-
ject
(Dual
J-K
Flip-
Flop
with
Reset
Nega-
tive-
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