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參數資料
| 型號： | 90USB82-16MU |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 48 MHz, RISC MICROCONTROLLER, QCC32 |
| 封裝： | 5 X 5 MM, GREEN, MO-220VHHD, QFN-32 |
| 文件頁數： | 5/8頁 |
| 文件大小： | 2816K |
| 代理商： | 90USB82-16MU |
5
7707A–AVR–03/07
AT90USB82/162
Pin Descriptions
VCC
Digital supply voltage.
GND
Ground.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the AT90USB82/162 as listed on
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of various special features of the AT90USB82/162 as listed on
Port D (PD7..PD0)
Port D serves as analog inputs to the analog comparator.
Port D also serves as an 8-bit bi-directional I/O port, if the analog comparator is not used (con-
cerns PD2/PD1 pins). Port pins can provide internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
D-/SDATA
USB Full Speed Negative Data Upstream Port / Data port for PS/2
D+/SCK
USB Full Speed Positive Data Upstream Port / Clock port for PS/2
UGND
USB Ground.
UVCC
USB Pads Internal Regulator Input supply voltage.
UCAP
USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac-
itor (1F).
RESET/PC1/dW
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page
47. Shorter pulses are not guaranteed to generate a reset. This pin alternatively serves as
debugWire channel or as generic I/O.
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2/PC0
Output from the inverting Oscillator amplifier if enabled by Fuse. Also serves as a generic I/O.
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