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參數資料
| 型號： | 9112AM-16LF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9112 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, MS-012, SOIC-8 |
| 文件頁數： | 5/8頁 |
| 文件大小： | 119K |
| 代理商： | 9112AM-16LF-T |
5
ICS9112A-16
1337K—08/03/07
Output to Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded
than CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause
them to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded Equally
REF input and CLK(1-4)
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLK(1_4)
outputs loaded equally, with
CLKOUT loaded Less.
Timing diagrams with different loading configurations
相關PDF資料 |
PDF描述 |
|---|---|
| 9112AM-16-T | 9112 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 9112AG-16 | 9112 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 9112AM-16 | 9112 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 9112AM-16LF | 9112 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 9112AG-16LF | 9112 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 9112AM-16LN | 制造商:Integrated Device Technology Inc 功能描述:IDT 9112AM-16LN PHASED LOCKED LOOP (PLL) - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:IDT 9112AM-16LN Phased Locked Loop (PLL) |
| 9112AM-16T | 制造商:INT_CIR_SYS 功能描述: |
| 9112AM-17LF | 功能描述:時鐘緩沖器 PC BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9112AM-17LFT | 功能描述:時鐘緩沖器 PC BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9112AM-26LF | 制造商:Integrated Device Technology Inc 功能描述:Clock Fanout Buffer 4-OUT 8-Pin SOIC N Tube 制造商:Integrated Device Technology Inc 功能描述:CLOCK BFFR 4-OUT 8SOIC - Rail/Tube |
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