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參數(shù)資料
| 型號： | 9147F-06 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 548K |
| 代理商： | 9147F-06 |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9147-06
Block Diagram
Pentium is a trademark of Intel Corporation
Frequency Generator & Integrated Buffers for PENTIUMTM
9147-06 RevA 5/29/97P
Pin Configuration
The ICS9147-06 generates all clocks required for high
speed RISC or CISC microprocessor systems such as Intel
PentiumPro. Two different reference frequency multiplying
factors are externally selectable with smooth frequency
transitions. Glitch-free Stop clock control is provided for
CPU and BUS clocks. Complete chip low current mode is
achieved with the Power Down# pin.
High drive BUS outputs typically provide greater than 1V/
ns slew rate into 30 pF loads. CPU outputs typically provide
better than 1V/ns slew rate into 20 pF loads while
maintaining 50±5% duty cycle. The REF and IOAPIC clock
outputs typically provide better than 0.5V/ns slew rates.
Separate buffer supply pins VDDL allow for nominal 3.3V
voltage or reduced voltage swing (from 2.9 to 2.5V) for
CPU (1:4) and IOAPIC outputs.
Generates five processor, eight bus, four 14.31818 MHz,
two 48 MHz clocks for USB support and one 24 MHz
clock.
CPU to BUS clock skew 1 to 4ns (CPU early)
Synchronous clocks skew matched to 250ps window on
CPU and 500ps window on BUS.
Selectable multiplying ratios
Glitch free stop clock controls CPUEN and BUSEN
3.0V 3.7V supply range, 2.5V to VDD supply range for
CPU (1:4) clocks and IOAPIC clock.
48-pin SSOP package
48-Pin SSOP
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
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