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參數(shù)資料
| 型號： | 9159N-05 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大小： | 228K |
| 代理商： | 9159N-05 |
2
ICS9159-05
Functionality
Assuming 14.318 MHz input, all frequencies
in MHz. 14 MHz=14.318 MHz
Notes:
1. 000 mode powers-down the PLL sections and forces the outputs low. To ensure glitch-free start and
stop of the CPU and BUS clocks, enter 000 from 001 and exit 000 through 001.
2. Select is FS0, Fs1 = 00, 01, 10, 11.
3. F is the value of CPU, ECPU & BUS. F value is 66.6, 60, 50 or 33.3 as selected by FS(0:1).
Notes:
1. Where F is Frequency selected by FS (0:1)
2. F value is 66.6, 60, 50 or 33.3.
STOP#
BSEL#
DOZE#
FS0
FS1
CPU (0:2)
(MHz)
ECPU
(MHz)
BUS
(0:5)
(MHz)
FIXED
(MHz)
1
0
1
0
1
0
1
0
1
0
X
Select
X
Select
X
F
F/2
Stop
Low
Tristate
F
F/2
Run
Stop
Low
Tristate
F
F/4
F/2
Run
Stop
Low
Tristate
24, 12, 14
L, L, 14
Tristate
STOP#
BSEL#
DOZE#
FS0
FS1
CPU (0:2)
(MHz)
ECPU
(MHz)
BUS
(0:5)
(MHz)
FIXED
(MHz)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Select
2
Select
2
Select
2
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Select
2
Select
2
Select
2
X
66.6
60
50
33.3
66.6
60
50
33.3
30
25
16.7
33.3
30
25
16.7
F
3
F/2
Stop
Low
Tristate
66.6
60
50
33.3
66.6
60
50
33.3
30
25
16.7
33.3
30
25
16.7
F
3
F/2
Run
Stop
Low
Tristate
33.3
30
25
16.7
66.6
60
50
33.3
16.7
15
12.5
8.3
33.3
30
25
16.7
F
3
F/2
Run
Stop
Low
Tristate
24, 12, 14
L, L, 14
Tristate
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