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參數資料
| 型號： | 9170-XXCS08 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數： | 7/12頁 |
| 文件大小： | 184K |
| 代理商： | 9170-XXCS08 |
4
AV9170
0237I—12/02/08
AV9170-05 is only available through America II distributor
1
S
F0
S
F1
K
L
C2
K
L
C
0
1
0
1
0
1
4
x
N
I
8
x
N
I
2
x
N
I
6
1
x
N
I
2
x
N
I
4
x
N
I
N
I
8
x
N
I
1
S
F0
S
F1
K
L
C2
K
L
C
0
1
0
1
0
1
2
x
N
I
4
x
N
I
N
I
8
x
N
I
N
I
2
x
N
I
2
÷
N
I
4
x
N
I
Figure 4:
Input and Output Clock Waveforms
with CLK2 Connected to FBIN
Using CLK2 Feedback
Connecting CLK2 to FBIN as shown in Figure 2 will cause
all of the rising edges to be aligned (Figure 4).
Figure 5:
Input and Output Clock Waveforms
with CLK1 Connected to FBIN
Table 2:
Functionality Table for AV9170-01, -
02 with CLK2 Feedback
Table 3:
Functionality Table for AV9170-01, -
02 with CLK1 Feedback
Using CLK1 Feedback
With CLK1 connected to FBIN as shown in Figure 3, the
input and CLK1 output will be aligned on the rising edge,
but CLK2 can be either rising or falling (Figure 5). Consult
ICS if the CLK1 frequency is desired to be higher than 107
MHz.
For CLK2 frequencies 10 - 53.5 MHz* (-01)
For CLK2 frequencies 2.5 - 13.37 MHz (-02)
*Maximum 33.3MHz @ 3.3V (-01), 8.33MHz @ 3.3V (-02)
Figure 2:
For CLK1 frequencies 20 - 107 MHz (-01)
For CLK1 frequencies 5 - 26.75 MHz (-02)
Maximum66.7MHz @ 3.3V(-01),16.7MHz @ 3.3V(-02)
Figure 3:
相關PDF資料 |
PDF描述 |
|---|---|
| 9170-XXCN08LF | 107 MHz, OTHER CLOCK GENERATOR, PDIP8 |
| 9170-XXCS08LF | 107 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 9170B-02CS08LF | 9170 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 9170B-01CS08LFT | 9170 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 9170B-01CS08LF | 9170 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
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