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參數(shù)資料
| 型號(hào)： | 91730AMLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9173 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, LEAD FREE, MS-012, SOIC-8 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 133K |
| 代理商： | 91730AMLFT |
5
ICS91730
0794E—06/04/08
Byte
0
Pin #
Name
Control Function
0
1
PWD
Bit 7
-
FS0
Spread/FS0
RW
1
Bit 6
-
FS1
Spread/FS1
RW
0
Bit 5
FS2
Spread/FS2
RW
0
Bit 4
FS3
Spread/FS3
RW
0
Bit 3
FS4
RW
0
Bit 2
PD# Tri_Sate
RW
Hi-Z
LOW
1
Bit 1
Spread Enable
RW
OFF
ON
1
Bit 0
HW/SW Control
Spread Spectrum Control
FS 3:4 Hard/Software
Select
RW
HW
SW
0
Byte
1
Pin #
Name
Control Function
0
1
PWD
Bit 7
REF_OUT
REF_OUT_Enable
RW
Disable
Enable
1
Bit 6
-
REF_OUT
Slew Rate REF-OUT
RW
Nominal
Fast
1
Bit 5
FS-IN_1
FS-IN_1 Readback
R
-
X
Bit 4
(Reserved)
R
-
0
Bit 3
CLK_OUT
Slew Rate CLK-OUT
RW
Nominal
Fast
1
Bit 2
CLK_OUT
CLK_OUT_Enable
RW
Disable
Enable
1
Bit 1
(Reserved)
R
-
1
Bit 0
(Reserved)
R-
-
1
Byte
2
Pin #
Name
Control Function
0
1
PWD
Bit 7
x
-
(Reserved)
-
1
Bit 6
x
(Reserved)
RW
Disable
Enable
1
Bit 5
x
(Reserved)
RW
Disable
Enable
1
Bit 4
x
(Reserved)
RW
Disable
Enable
1
Bit 3
x
(Reserved)
RW
Disable
Enable
1
Bit 2
x
(Reserved)
RW
Disable
Enable
1
Bit 1
x
(Reserved)
RW
Disable
Enable
1
Bit 0
x
(Reserved)
RW
Disable
Enable
1
Affected Pin
Srpead Pecentage
See Table1
These are I2C bits
only
Type
Bit Control
Type
Bit Control
Type
Bit Control
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 91730AMLF | 9173 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 91730YMLFT | 91730 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 9173B-15CS08LF | 37.5 MHz, VIDEO CLOCK GENERATOR, PDSO8 |
| 9173B-15CS08LFT | 37.5 MHz, VIDEO CLOCK GENERATOR, PDSO8 |
| 9176CM-03 | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
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參數(shù)描述 |
|---|---|
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