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參數資料
| 型號： | 9176M-01 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數： | 3/8頁 |
| 文件大?。?/td> | 379K |
| 代理商： | 9176M-01 |
3
ICS9176-01
Timing Diagrams
Note: In test mode, the VCOs are bypassed. The test clock input is simply buffered, then output. The part is transparent. Damage
to the device may occur if an output is shorted or forced to ground or VDD.
Timing in Power-down Mode
Timing in Eliminate by Test Mode
Timing in Divide by 2 Mode
Timing in Divide by 1 Mode
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