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參數(shù)資料
| 型號： | 91857AGT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 91857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 164K |
| 代理商： | 91857AGT |
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91857A (DDR PLL)
Description
2.5 Wide Range Frequency Clock Driver
Market Group
DIMM
Additional Info
Meets PC3200 specification for DDRI-400 support Low skew, low jitter PLL clock driver 1 to 10 differential clock distribution (SSTL_2)
Feedback pins for input to output synchronization PD# for power management Spread Spectrum tolerant inputs Auto PD when input signal
removed
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Related Orderable Parts
Attributes
91857AG
91857AGLF
91857AGLFT
91857AGT
91857AL
91857ALT
Package
TSSOP 48 (PA48)
TSSOP 48 (PAG48)
TSSOP 48 (PA48)
TVSOP 48 (PF48)
Speed
NA
Temperature
C
Voltage
3.3 V
Status
Active
Sample
No
Minimum Order
Quantity
380
1000
384
1000
Factory Order
Increment
38
1000
48
1000
Related Documents
Type
Title
Size
Revision Date
Datasheet
91857A
134 KB
03/22/2006
Product Change Notice
PCN#: TB-0510-05 New Shipping Tube for TSSOP/TVSOP/TSSOP Exposed
202 KB
12/13/2005
Page 1 of 2
08-Jun-2007
mhtml:file://C:\91857A.mht
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 91857AG-LF | 91857 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
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