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參數資料
| 型號： | 9248YF-112-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 202K |
| 代理商： | 9248YF-112-T |
Integrated
Circuit
Systems, Inc.
ICS9248-112
0326C—09/18/03
Block Diagram
Recommended Application:
810/810E type chipset.
Output Features:
2- CPUs @2.5V, up to 166.5MHz.
9 - SDRAM @ 3.3V, up to150MHz including
1 free running
8 - PCICLK @ 3.3V
1 - IOAPIC @ 2.5V, PCI or PCI/2 MHz
2 - 3V66MHz @ 3.3V, 2X PCI MHz
1- 48MHz, @3.3V fixed.
1- 24MHz, @3.3V fixed
1- REF @3.3V, 14.318MHz.
Features:
Up to 166MHz frequency support
Support FS0-FS3 strapping status bit for I
2C read
back.
Support power management: Through Power down
Mode from I
2C programming.
Spread spectrum for EMI control ( ± 0.25% center).
Spread can be enabled or disabled to all 32
frequencies throuth I
2C.
Uses external 14.318MHz crystal
Skew Specifications:
CPU – CPU: <175ps
SDRAM - SDRAM: < 250ps
3V66 – 3V66: <175ps
PCI – PCI: <500ps
CPU-SDRAM<500ps
For group skew specifications, please refer to group
timing relationship table.
Functionality
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD.
1. These are double strength.
[1:0]
Frequency Generator & Integrated Buffers for Celeron & PII/III
Additional
frequencies
selectable
through
I
2C
programming.
3
S
F2
S
F1
S
F0
S
F
U
P
C
)
z
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(
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A
R
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I
C
P
)
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(
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I
P
A
O
I
2
/
K
L
C
I
C
P
=
1
)
z
H
M
(
C
I
P
A
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I
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L
C
I
C
P
=
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)
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.
6
60
2
.
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.
6
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4
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7
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6
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3
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0
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8
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0
.
2
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10
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8
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4
30
0
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7
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4
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.
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0
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8
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6
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4
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3
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7
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3
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3
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3
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4
37
1
.
7
13
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3
10
0
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0
4
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0
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5
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0
70
0
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5
30
5
.
7
10
0
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5
3
10
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1
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.
0
4
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0
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4
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2
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3
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1
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6
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0
23
3
.
1
4
11
0
7
.
3
10
7
.
3
13
1
.
9
87
5
.
4
48
2
.
2
27
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7
3
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3
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1
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6
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5
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2
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