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參數資料
| 型號： | 9248YG-92GLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 557K |
| 代理商： | 9248YG-92GLFT |
ICS9248-92
IDTTM Mobile Pentium IITM System Clock Chip
309—01/25/10
Mobile Pentium IITM System Clock Chip
1
DATASHEET
Recommended Application:
The ICS9248-92 is a fully compliant timing solution for the
Intel mobile 440BX/MX chipset requirements.
General Description:
Features include two strong CPU, seven PCI and eight SDRAM
clocks. Three reference outputs are available equal to the
crystal frequency. Stronger drive CPUCLK outputs typically
provide greater than 1 V/ns slew rate into 20pF loads. This
device meets rise and fall requirements with 2 loads per CPU
output (ie, one clock to CPU and NB chipset, one clock to two
L2 cache inputs).
PWR_DWN# pin allows low power mode by stopping crystal
OSC and PLL stages. For optional power management,
CPU_STOP# can stop CPU (0:1) clocks and PCI_STOP# will
stop PCICLK (0:5) clocks.
PCICLK outputs typically provide better than 1V/ns slew rate
into 30pF loads while maintaining 50±5% duty cycle. The REF
clock outputs typically provide better than 0.5V/ns slew rates.
The ICS9248-92 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Features:
Generates system clocks for CPU, SDRAM, PCI, plus
14.318 MHz REF(0:2), USB, Plus Super I/O
I2C serial configuration interface provides output clock
disabling and other functions
MODE input pin selects optional power management
input control pins
Two fixed outputs separately selectable as 24 or 48MHz
2.5V outputs: CPU
3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
No power supply sequence requirements
Uses external 14.318MHz crystal
48 pin 240 mil TSSOP package
Output enable register for serial port control: 1 = enable
0 = disable
Block Diagram
Pin Configuration
Functionality
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