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參數資料
| 型號： | 9250BF-28 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 133.32 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, SSOP-56 |
| 文件頁數： | 1/19頁 |
| 文件大小： | 226K |
| 代理商： | 9250BF-28 |
Integrated
Circuit
Systems, Inc.
ICS9250-28
Third party brands and names are the property of their respective owners.
Block Diagram
9250-28 Rev B 10/26/00
Recommended Application:
810/810E and 815 type chipset.
Output Features:
2 CPU (2.5V) (up to 133MHz achievable through I
2C)
13 SDRAM (3.3V) (up to 133MHz achievable
through I
2C)
2 PCI (3.3 V) @33.3MHz
1 IOAPIC (2.5V) @ 33.3 MHz
3 Hublink clocks (3.3 V) @ 66.6 MHz
2 (3.3V) @ 48 MHz (Non spread spectrum)
1 REF (3.3V) @ 14.318 MHz
Features:
Supports spread spectrum modulation,
0 to -0.5% down spread.
I
2C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Alternate frequency selections available through I
2C
control.
Functionality
Pin Configuration
56-Pin 300mil SSOP
* This input has a 50K
W pull-down to GND.
IOAPIC
VDDL
GND
*FS1/REF0
VDDREF
X1
X2
GND
VDD3V66
3V66_0
3V66_1
3V66_2
GND
VDDPCI
PCICLK0
PCICLK1
GND
FS0
GND
VDDA
PD#
SCLK
SDATA
GND
VDD48
48MHz_0
48MHz_1
FS2
VDDL
GND
CPUCLK0
CPUCLK1
GND
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
SDRAM4
VDDSDR
GND
SDRAM5
SDRAM6
VDDSDR
GND
SDRAM7
SDRAM8
SDRAM9
VDDSDR
GND
SDRAM10
SDRAM11
VDDSDR
GND
SDRAM12
ICS9250-28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Frequency Generator & Integrated Buffers for Celeron & PII/III
2
S
F0
S
F1
S
Fn
o
i
t
c
n
u
F
00
X
e
t
a
t
s
i
r
T
01
X
t
s
e
T
10
0
z
H
M
6
=
U
P
C
e
v
i
t
c
A
z
H
M
0
1
=
M
A
R
D
S
11
0
z
H
M
0
1
=
U
P
C
e
v
i
t
c
A
z
H
M
0
1
=
M
A
R
D
S
10
1
z
H
M
3
1
=
U
P
C
e
v
i
t
c
A
z
H
M
3
1
=
M
A
R
D
S
11
1
z
H
M
3
1
=
U
P
C
e
v
i
t
c
A
z
H
M
0
1
=
M
A
R
D
S
REF0
CPU66/100/133 [1:0]
3V66 (2:0)
SDRAM (12:0)
PCICLK (1:0)
IOAPIC
PLL2
48MHz (1:0)
X1
X2
XTAL
OSC
Control
Logic
Config
Reg
FS(2:0)
PD#
2
3
13
2
/2
/3
/2
PLL1
Spread
Spectrum
SDATA
SCLK
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Power Groups
Analog
VDDREF = X1, X2
VDDA = PLL1
VDD48 = PLL2
Digital
VDD3V66, VDDPCI
VDDSDR, VDDL
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 9250BF-28LF | 制造商:Integrated Device Technology Inc 功能描述:PLL Frequency Generator Single 56-Pin SSOP Tube |
| 9250BF-28LFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Frequency Generator Single 56-Pin SSOP T/R |
| 9250BFI-27LF | 功能描述:時鐘發生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9250BFI-27LFT | 功能描述:時鐘發生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9250CF-08LF | 制造商:Integrated Device Technology Inc 功能描述:IDT 9250CF-08LF PHASED LOCKED LOOP (PLL) - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:IDT 9250CF-08LF Phased Locked Loop (PLL) |
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