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參數資料
| 型號： | 933282430652 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 多路復用及模擬開關 |
| 英文描述： | 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDIP16 |
| 封裝： | PLASTIC, SOT-38, DIP-16 |
| 文件頁數： | 2/9頁 |
| 文件大小： | 117K |
| 代理商： | 933282430652 |
January 1995
2
Philips Semiconductors
Product specication
Dual 4-channel analogue multiplexer/demultiplexer
HEF4052B
MSI
DESCRIPTION
The HEF4052B is a dual 4-channel
analogue multiplexer/demultiplexer
with common channel select logic.
Each multiplexer/demultiplexer has
four independent inputs/outputs
(Y0 to Y3) and a common input/output
(Z). The common channel select logic
includes two address inputs (A0 and
A1) and an active LOW enable input
(E).
Both multiplexers/demultiplexers
contain four bidirectional analogue
switches, each with one side
connected to an independent
input/output (Y0 to Y3) and the other
side connected to a common
input/output (Z).
With E LOW, one of the four switches
is selected (low impedance ON-state)
by A0 and A1. With E HIGH, all
switches are in the high impedance
OFF-state, independent of A0 and A1.
VDD and VSS are the supply voltage
connections for the digital control
inputs (A0,A1 and E). The VDD to
VSS range is 3 to 15 V. The analogue
inputs/outputs (Y0 to Y3, and Z) can
swing between VDD as a positive limit
and VEE as a negative limit.
VDD VEE may not exceed 15 V.
For operation as a digital
multiplexer/demultiplexer, VEE is
connected to VSS (typically ground).
Fig.1 Functional diagram.
PINNING
FAMILY DATA,
IDD LIMITS category MSI
See Family Specifications
Y0A to Y3A
independent inputs/outputs
Y0B to Y3B
independent inputs/outputs
A0, A1
address inputs
E
enable input (active LOW)
ZA, ZB
common inputs/outputs
HEF4052BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4052BD(F): 16-lead DIL; ceramic
(cerdip)
(SOT74)
HEF4052BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
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