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參數資料
| 型號： | 933836090005 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 多路復用及模擬開關 |
| 英文描述： | TRIPLE 2-CHANNEL, SGL ENDED MULTIPLEXER, UUC |
| 文件頁數： | 7/16頁 |
| 文件大?。?/td> | 124K |
| 代理商： | 933836090005 |
December 1990
15
Philips Semiconductors
Product specication
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
TEST CIRCUIT AND WAVEFORMS
Fig.21 Test circuit for measuring AC performance.
Conditions
TEST
SWITCH
Vis
tPZH
tPZL
tPHZ
tPLZ
others
VEE
VCC
VEE
VCC
open
VCC
VEE
VCC
VEE
pulse
FAMILY
AMPLITUDE
VM
tr;tf
fmax;
PULSE WIDTH
OTHER
74HC
VCC
50%
< 2 ns
6 ns
74HCT
3.0 V
1.3 V
< 2 ns
6 ns
CL
=
load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values).
RT
=
termination resistance should be equal to the output impedance ZO of the pulse generator.
tr
=tf = 6 ns; when measuring fmax, there is no constraint on tr, tf with 50% duty factor.
Fig.22 Input pulse definitions.
Conditions
TEST
SWITCH
Vis
tPZH
tPZL
tPHZ
tPLZ
others
VEE
VCC
VEE
VCC
open
VCC
VEE
VCC
VEE
pulse
FAMILY
AMPLITUDE
VM
tr;tf
fmax;
PULSE WIDTH
OTHER
74HC
VCC
50%
< 2 ns
6 ns
74HCT
3.0 V
1.3 V
< 2 ns
6 ns
CL
=
load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values).
RT
=
termination resistance should be equal to the output impedance ZO of the pulse generator.
tr
=tf = 6 ns; when measuring fmax, there is no constraint on tr, tf with 50% duty factor.
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