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參數(shù)資料
| 型號： | 934055349118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | 19 A, 55 V, 0.075 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | DPAK-3 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 147K |
| 代理商： | 934055349118 |
Philips Semiconductors
Product specification
N-channel TrenchMOS
transistor
PHP21N06LT, PHB21N06LT
Logic level FET
PHD21N06LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
’Trench’ technology
V
DSS = 55 V
Low on-state resistance
Fast switching
I
D = 19 A
Logic level compatible
R
DS(ON) ≤ 75 m (VGS = 5 V)
R
DS(ON) ≤ 70 m (VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
d.c. to d.c. converters
switched mode power supplies
The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB21N06LT is supplied in the SOT404 (D
2PAK) surface mounting package.
The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404 (D
2PAK)
SOT428 (DPAK)
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j = 25 C to 175C
-
55
V
DGR
Drain-gate voltage
T
j = 25 C to 175C; RGS = 20 k
-55
V
GS
Gate-source voltage
-
± 15
V
GSM
Pulsed gate-source voltage
T
j ≤ 150C
-
± 20
V
I
D
Continuous drain current
T
mb = 25 C
-
19
A
T
mb = 100 C
-
13
A
I
DM
Pulsed drain current
T
mb = 25 C
-
76
A
P
D
Total power dissipation
T
mb = 25 C
-
56
W
T
j, Tstg
Operating junction and
- 55
175
C
storage temperature
d
g
s
12 3
tab
13
tab
2
1
2
3
tab
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
August 1999
1
Rev 1.500
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