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參數(shù)資料
| 型號： | 934055351118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | 50 A, 55 V, 0.024 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 118K |
| 代理商： | 934055351118 |
Philips Semiconductors
Product specification
TrenchMOS
transistor
PHP50N06LT, PHB50N06LT, PHD50N06LT
Logic level FET
FEATURES
SYMBOL
QUICK REFERENCE DATA
’Trench’ technology
V
DSS = 55 V
Very low on-state resistance
Fast switching
I
D = 50 A
Stable off-state characteristics
High thermal cycling performance
R
DS(ON) ≤ 24 m (VGS = 5 V)
Low thermal resistance
R
DS(ON) ≤ 22 m (VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP50N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB50N06LT is supplied in the SOT404 surface mounting package.
The PHD50N06LT is supplied in the SOT428 surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404
SOT428
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j = 25 C to 175C
-
55
V
DGR
Drain-gate voltage
T
j = 25 C to 175C; RGS = 20 k
-55
V
GS
Gate-source voltage
-
± 13
V
I
D
Continuous drain current
T
mb = 25 C
-
50
A
T
mb = 100 C
-
35
A
I
DM
Pulsed drain current
T
mb = 25 C
-
200
A
P
D
Total power dissipation
T
mb = 25 C
-
125
W
T
j, Tstg
Operating junction and
- 55
175
C
storage temperature
d
g
s
1
2
3
tab
13
tab
2
12 3
tab
1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
September 1998
1
Rev 1.400
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