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參數資料
| 型號： | 935020320112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | PLASTIC, SO-24 |
| 文件頁數： | 17/18頁 |
| 文件大小： | 96K |
| 代理商： | 935020320112 |
1996 Aug 26
8
Philips Semiconductors
Product specication
8-bit high-speed analog-to-digital converter
TDA8703
Reference resistance
Rref
reference resistance
VRT to VRB
220
Outputs
DIGITAL OUTPUTS (D7 - D0) (REFERENCED TO DGND)
VOL
LOW level output voltage
IO = 1 mA
0
0.4
V
VOH
HIGH level output voltage
IO = 0.4 mA
2.7
VCCD
V
IOZ
output current in 3-state mode
0.4 V
< VO < VCCD
20
+20
A
Switching characteristics (note 2; see Fig.3)
fCLK/fCLK
maximum clock frequency
40
MHz
Analog signal processing (fCLK = 40 MHz)
B
3 dB bandwidth
note 3
19.5
MHz
Gd
differential gain
note 4
0.6
%
φd
differential phase
note 4
0.8
deg
f1
fundamental harmonics (full-scale)
fi = 4.43 MHz
0dB
fall
harmonics (full-scale), all components
fi = 4.43 MHz
55
dB
SVRR1
supply voltage ripple rejection
note 5
28
25
dB
SVRR2
supply voltage ripple rejection
note 5
1
2.5
%/V
Transfer function
ILE
DC integral linearity error
±1
LSB
DLE
DC differential linearity error
±1/2
LSB
AILE
AC integral linearity error
note 6
±2
LSB
EB
effective bits
fi = 4.43 MHz
7.1
bits
Timing (note 7; see Figs 3 to 6; fCLK = 40 MHz)
tdS
sampling delay
2ns
tHD
output hold time
6
ns
tdLH
output delay time
LOW-to-HIGH transition
810
ns
tdHL
output delay time
HIGH-to-LOW transition
16
20
ns
tdZH
3-state output delay times
enable-to-HIGH
19
25
ns
tdZL
3-state output delay times
enable-to-LOW
16
20
ns
tdHZ
3-state output delay times
disable-to-HIGH
14
20
ns
tdLZ
3-state output delay times
disable-to-LOW
912
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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