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參數資料
| 型號： | 935020320118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | PLASTIC, SO-24 |
| 文件頁數： | 12/18頁 |
| 文件大?。?/td> | 96K |
| 代理商： | 935020320118 |
1996 Aug 26
3
Philips Semiconductors
Product specication
8-bit high-speed analog-to-digital converter
TDA8703
QUICK REFERENCE DATA
Notes
1. Full-scale sinewave (fi = 4.4 MHz; fCLK; fCLK = 27 MHz).
2. The
3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at input).
3. The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the LOW-to-HIGH transition of the input clock signal.
b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the HIGH-to-LOW transition of the input clock signal.
c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.
d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
analog supply voltage
4.5
5.0
5.5
V
VCCD
digital supply voltage
4.5
5.0
5.5
V
VCCO
output stages supply voltage
4.2
5.0
5.5
V
ICCA
analog supply current
28
36
mA
ICCD
digital supply current
19
25
mA
ICCO
output stages supply current
11
14
mA
ILE
DC integral linearity error
±1
LSB
DLE
DC differential linearity error
±1/2
LSB
AILE
AC integral linearity error
note 1
±2
LSB
B
3 dB bandwidth
note 2; fCLK = 40 MHz
19.5
MHz
fCLK/fCLK
maximum conversion rate
note 3
40
MHz
Ptot
total power dissipation
290
415
mW
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