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參數(shù)資料
| 型號： | 935050700112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), EQUALIZER CIRCUIT, PDIP32 |
| 封裝： | PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 17/19頁 |
| 文件大小： | 212K |
| 代理商： | 935050700112 |
May 1991
7
Philips Semiconductors
Preliminary specication
5-band stereo equalizer circuit
TEA6360
VN
weighted output noise voltage
CCIR 468-3, maximum
(RMS value)
gain/lter of 12 dB
defeat mode
816
V
all lters linear
23
46
V
all lters maximum boost
70
140
V
all lters maximum cut
23
46
V
αCr
crosstalk between bus inputs and signal
outputs, 20 log (Vbus(p-p)/Vo rms)
all lters linear
120
dB
RR
ripple rejection at Vripple rms < 200 mV
all lters linear
for f = 100 Hz
70
dB
for f = 40 to 12500 Hz
60
dB
Internal lters of analog part
Q
Q-factor dependent on maximum gain
maximum gain 10 dB
0.1
1.2
maximum gain 12 dB
0.1
1.4
maximum gain 15 dB
0.1
1.8
Rtot
total resistor of different lter sections
29.6
37.0
44.4
k
Rtot
tolerance between any lter section
± 4%
Internal controls of analog part via I2C-bus
Step
number of steps for boost or for cut
5
position for linear
1
step resolution
maximum gain 12 dB
2.4
dB
step set error
0.5
dB
Vo
DC offset between any step or
neighbouring step or defeat
±10
mV
I2C-bus control SDA and SCL (pins 15 and 16)
VIH
input level HIGH
3
VP
V
VlL
input level LOW
0
1.5
V
II
input current
±10
A
VACK
acknowledge voltage on SDA
l15 = 3 mA at LOW
0.4
V
Module address bit (pin 18)
VIH
input level HIGH for address 1000 0110
3
Vp
V
VIL
input level LOW for address 1000 0100
0
1.5
V
II
input current
±10
A
Power on reset: When reset is active the DEF-bit (defeat) is set and the I2C-bus receiver is in reset position.
RESET
start of reset
increasing VP
2.5
V
decreasing VP
4.2
5.0
5.8
V
end of reset
increasing VP
5.2
6.0
6.8
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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