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參數資料
| 型號： | 935057010602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發器 |
| 英文描述： | ABT SERIES, 10 1-BIT DRIVER, TRUE OUTPUT, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數： | 1/6頁 |
| 文件大?。?/td> | 69K |
| 代理商： | 935057010602 |
Philips Semiconductors
Product specification
74ABT841
10-bit bus interface latch (3-State)
1
1995 Sep 06
853-1628 15703
FEATURES
High speed parallel latches
Extra data width for wide address/data paths or buses carrying
parity
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Slim DIP 300 mil package
Broadside pinout
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power-up 3-State
Power-up reset
DESCRIPTION
The 74ABT841 Bus interface register is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT841 consists of ten D-type latches with 3-State outputs.
The flip-flops appear transparent to the data when Latch Enable
(LE) is High. This allows asynchronous operation, as the output
transition follows the data in transition. On the LE High-to-Low
transition, the data that meets the setup and hold time is latched.
Data appears on the bus when the Output Enable (OE) is Low.
When OE is High the output is in the High-impedance state.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25°C; GND = 0V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
Dn to Qn
CL = 50pF; VCC = 5V
4.1
ns
CIN
Input capacitance
VI = 0V or VCC
4
pF
COUT
Output capacitance
Outputs disabled;
VO = 0V or VCC
7
pF
ICCZ
Total supply current
Outputs disabled; VCC = 5.5V
500
nA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
24-Pin Plastic DIP
–40
°C to +85°C
74ABT841 N
SOT222-1
24-Pin plastic SO
–40
°C to +85°C
74ABT841 D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°C to +85°C
74ABT841 DB
SOT340-1
24-Pin Plastic TSSOP Type I
–40
°C to +85°C
74ABT841 PW
74ABT841PW DH
SOT355-1
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
15
16
17
18
19
20
21
22
23
24
OE
D0
D1
D2
D3
D4
D5
D6
D7
Q7
D8
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
Q8
11
14
D9
Q9
12
13
GND
LE
TOP VIEW
SA00247
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
OE
Output enable input
(active-Low)
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
D0-D9
Data inputs
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
Q0-Q9
Data outputs
13
LE
Latch enable input (active
falling edge)
12
GND
Ground (0V)
24
VCC
Positive supply voltage
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