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參數資料
| 型號： | 935077580157 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, SOT-318, QFP-80 |
| 文件頁數： | 3/30頁 |
| 文件大?。?/td> | 230K |
| 代理商： | 935077580157 |
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1996 Oct 25
11
Philips Semiconductors
Preliminary specication
Progressive scan-Zoom and Noise
reduction IC (PROZONIC)
SAA4990H
Control and microcontroller (SNERT-) interface
CONTROL SIGNALS
CK
Line-locked clock of nominal 27 or 32 MHz. This is the
system clock, nominally 864 or 1024
× fh, where fh is the
line frequency. Within the PROZONIC, CK is distributed to
different blocks.
HD
Horizontal reference signal. This signal defines with its
rising edge the start phase of the UV 4 :1:1 format. If the
HD signal has a period equal to 4 clock periods, the UV
data will remain in phase without disruptions, once it has
become in phase. For any mismatch between the applied
HD to the UV data phase, an appropriate HD delay can be
set in the PROZONIC. HD is also used to count lines for
boxing.
RE
Master read enable from memory controller or
ECOBENDIC. This signal controls the memory read
enable if only one field memory is present. To control two
field memories, the PROZONIC generates RE1, RE2 and
WE2 from RE. The vertical sample rate conversion
function has a major influence on these signals.
RE1
Read enable for FM1, processed from RE by PROZONIC.
Fig.7 Box dimensions and position.
handbook, halfpage
MGE033
,,,,,
hor_start_box
vert_start_box
vert_stop_box
hor_stop_box
RE2
Read enable for FM2, processed from RE by PROZONIC.
WE2
Write enable for FM2, processed from RE by PROZONIC.
HO
Holds the writing of the LC display when active.
AUX
Spare output from line-sequencer.
VD
Field frequent reset signal, used in PROZONIC to reset
line counting for boxing. The rising edge of VD is taken as
reference. This may be the display related vertical pulse.
SNRST
Field frequent asynchronous reset signal, used in
PROZONIC to reset the communication with
microcontroller. After the rising edge of SNRST,
communication is in its defined state. SNRST is also used
to define the initial phase of the line-sequencer.
SNCL
microcontroller interface clock signal. This signal is
transferred asynchronous to CK by a microcontroller
(UART of 8051 family, mode 0) as communication clock
signal at a frequency of 1 MHz.
SNDA
microcontroller interface data signal. This signal is
transferred or received (asynchronous to CK) by a
microcontroller (UART of 8051 family, mode 0) as
communication data signal at 1 MBaud, related to SNCL.
EXTERNAL CONTROL
The PROZONIC is controlled via the microcontroller
(SNERT) interface, by sending an address byte and a data
byte to it, with the controllable items as in the register
descriptions in Tables 2 and 3.
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