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參數資料
| 型號： | 935176920112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 畫面疊加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDSO24 |
| 封裝： | PLASTIC, SOT-137-1, SO-24 |
| 文件頁數： | 41/66頁 |
| 文件大?。?/td> | 445K |
| 代理商： | 935176920112 |
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1995 Jan 19
46
Philips Semiconductors
Preliminary specication
Stand-alone OSD
PCA8515
11 OSD CLOCK
The on-chip clock generator comprises Phase-Locked
Loop circuitry and is shown in Fig.39. The frequency of the
OSD clock is programmable and is determined by the
contents of the 6-bit counter, which is loaded using
Command 6. The OSD clock frequency is calculated as
shown below; frequencies within the range 4 to10 MHz
can be selected.
Where: 16 < (PLLCN) < 40; (PLLCN) is the decimal value
held in the 6-bit counter.
The Voltage Controlled Oscillator (VCO) is synchronized
to the HIGH-to-LOW edge of f1 (see Fig.39) which is
always on the traiing edge of fHSYNC. The programmable
active level detector will pass the HSYNC signal if it is
programmed as active HIGH or invert the HSYNC signal if
it is programmed as active LOW. The 4-bit prescaler
increments or decrements the output of the VCO in steps
of (16
× fHSYNC).
f
OSD
f
HSYNC
16
PLLCN
()
×
=
The OSD clock is enabled/disabled using Command 7;
see Section 9.8. When the OSD clock is disabled, the
oscillator remains active, therefore the transient time from
the OSD clock start-up to locking into the external HSYNC
signal is reduced. As the on-chip oscillator is always active
after power-on, when the OSD clock is enabled no large
currents flow (as for RC or LC oscillators); therefore
radiated noise is dramatically reduced.
Character width is a function of the OSD clock frequency;
decreasing fOSD increases the width of the characters.
Therefore, for optimum character display quality the
choice of the OSD clock frequency is important; this is
explained in Chapter 12.
Fig.39 Block diagram of OSD oscillator.
handbook, full pagewidth
MLC349
VOLTAGE
CONTROLLED
OSCILLATOR
CHARGE PUMP
AND
LOOP FILTER
PHASE/
FREQUENCY
DETECTOR
ACTIVE
LEVEL
DETECTOR
PROGRAMMABLE
6-BIT COUNTER
f OSD
divided by N
4-BIT
PRESCALER
HSYNC
OSD disable
f PLL
f 1
C
R1
C1
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