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參數資料
| 型號： | 935187510112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 多路復用及模擬開關 |
| 英文描述： | QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO14 |
| 封裝： | 4.40 MM, PLASTIC, TSSOP-14 |
| 文件頁數： | 12/24頁 |
| 文件大小： | 139K |
| 代理商： | 935187510112 |
1998 Nov 10
2
Philips Semiconductors
Product specication
Quad bilateral switches
74HC/HCT4066
FEATURES
Very low “ON” resistance:
50
(typ.) at VCC = 4.5 V
45
(typ.) at VCC = 6.0 V
35
(typ.) at VCC = 9.0 V
Output capability: non-standard
ICC category: SSI.
GENERAL DESCRIPTION
The 74HC/HCT4066 are high-speed Si-gate CMOS
devices and are pin compatible with the “4066” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4066 have four independent analog
switches. Each switch has two input/output terminals (nY,
nZ) and an active HIGH enable input (nE). When nE is
LOW the belonging analog switch is turned off.
The “4066” is pin compatible with the “4016” but exhibits a
much lower “ON” resistance. In addition, the “ON”
resistance is relatively constant over the full input signal
range.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf =6ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
a) PD =CPD × VCC2 × fi +∑ {(CL + CS)× VCC2 × fo} where:
b) fi = input frequency in MHz
c) fo = output frequency in MHz
d)
∑ {(CL + CS)× VCC2 × fo} = sum of outputs
e) CL = output load capacitance in pF
f) CS = maximum switch capacitance in pF
g) VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPZH/ tPZL
turn-on time nE to Vos
CL = 15 pF; RL =1k; VCC = 5 V 11
12
ns
tPHZ/ tPLZ
turn-off time nE to Vos
13
16
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per switch
notes 1 and 2
11
12
pF
CS
max. switch capacitance
8
pF
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