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參數(shù)資料
型號： 935193810112
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDIP56
封裝： 0.600 INCH, PLASTIC, SOT-400, SDIP-56
文件頁數(shù)： 26/75頁
文件大小： 522K
代理商： 935193810112
1997 Jul 01
32
Philips Semiconductors
Preliminary specication
I2C-bus controlled economy PAL/NTSC
and NTSC TV-processors
TDA837x family
td(blank,RGB) delay difference of blanking and
RGB signals
note 4
50
ns
tsw
switching speed of blanking
circuit
10
ns
I26
input current
0.2
mA
SSint
suppression of internal RGB
signals
insertion; fi = 0 to 5 MHz;
notes 4 and 22
55
dB
SSext
suppression of external RGB
signals
no insertion;
fi = 0 to 5 MHz;
notes 4 and 22
55
dB
Vi
input voltage to insert black level
at the RGB outputs to facilitate
‘On Screen Display’ signals
being applied to the outputs
4
V
td(blank-RGB)
delay between blanking input
and RGB outputs
80
ns
COLOUR DIFFERENCE INPUT SIGNALS (PINS 31 AND 32)
V31(p-p)
input signal amplitude (R
Y)
(peak-to-peak value)
note 2
1.05
V
V32(p-p)
input signal amplitude (B
Y)
(peak-to-peak value)
note 2
1.35
V
I31,32
input current for both inputs
note 2
0.1
1.0
A
LUMINANCE INPUTS AND OUTPUTS (PINS 27 AND 28); note 25
V27,28
output signal amplitude
(black-to-white)
1
V
Chrominance lters
CHROMINANCE TRAP CIRCUIT; note 26
ftrap
trap frequency
fosc
MHz
QF
trap quality factor
note 27
2
CSR
colour subcarrier rejection
20
dB
ftrap(SECAM)
trap frequency
during SECAM reception
4.3
MHz
CHROMINANCE BAND-PASS CIRCUIT
fc
centre frequency
1.1fosc
MHz
Qbp
band-pass quality factor
3
Luminance processing
Y DELAY LINE
td(Y)
delay time
note 4
480
ns
Bdel(int)
bandwidth of internal delay line
note 4
8
MHz
PEAKING CONTROL; note 28
tW
width of preshoot or overshoot
at 50% of pulse; note 8
160
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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