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參數(shù)資料
| 型號： | 935247880557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 畫面疊加 |
| 英文描述： | PICTURE-IN-PICTURE IC, PQFP100 |
| 封裝： | PLASTIC, SOT-317-2, QFP-100 |
| 文件頁數(shù)： | 10/35頁 |
| 文件大小： | 273K |
| 代理商： | 935247880557 |
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1996 Aug 13
18
Philips Semiconductors
Preliminary specication
Picture-In-Picture (PIP) controller
SAB9076H
Table 5
Colour types and brightness levels
COLOUR TYPE
BRIGHTNESS LEVEL
COLOUR
VALUE
4H
5H
6H
7H
Black
0H
0%
10%
30%
50%
Blue
1H
30%
50%
70%
100%
Red
2H
30%
50%
70%
100%
Magenta
3H
30%
50%
70%
100%
Green
4H
30%
50%
70%
100%
Cyan
5H
30%
50%
70%
100%
Yellow
6H
30%
50%
70%
100%
White
7H
60%
70%
80%
100%
Table 5 indicates how I2C-bus register settings control the
colour and brightness. All colour registers are similar, they
contain one on/off bit, two brightness bits and three colour
type bits. To determine which colour is visible in the event
two or more colours being displayed on the same position,
the next priority scheme is followed.
1. Sub-select colour (SBS)
2. Sub-border colour (SB)
3. Main-select colour (MBS)
4. Main-border colour (MB)
5. Background colour (BG).
SA 15H AND SA 16H DECODER REGISTERS
The MVFILT and SVFILT bits can set the type of vertical
filtering. The MUVPOL and SUVPOL bits invert the UV
polarity of the incoming signals. The MVSPOL and
SVSPOL bits determine the active edge of the Vsync (see
Fig.7). MHSYNC and SHSYNC bits determine the timing
of the Hsync pulse (burstkey or Hsync timing). The MFPOL
and SFPOL bits can invert the field identification (ID) of the
incoming fields (see Fig.7).
SA 17H DISPLAY SETTINGS REGISTER
The FBDEL2 to FBDEL0 bits can adjust the fast blank
delay in 8 steps of 1
2 a clock cycle (8 to +7). 0H is
mid-scale. The DUVPOL bit inverts the UV polarity of the
border colours.
The DVSPOL bit determines the active edge of the Vsync
(see Fig.7). The DHSYNC bit determines the timing of the
Hsync pulse (burstkey or Hsync). The DFPOL bit can invert
the field identification of the incoming fields (see Fig.7).
SA 18H PEDESTAL SETTINGS REGISTER
The PEDESTU3 to PEDESTU0 and
PEDESTV3 to PEDESTV0 bits provide the U and V DAC
outputs an offset of
8 to +7 LSB when the FBL is
switched off. This can be used to adjust the white point of
the system.
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