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參數資料
型號: 935260050112
廠商: NXP SEMICONDUCTORS
元件分類: 多路復用及模擬開關
英文描述: QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO14
封裝: PLASTIC, SOT-108, SO-14
文件頁數: 6/8頁
文件大小: 85K
代理商: 935260050112
January 1995
6
Philips Semiconductors
Product specication
Quadruple bilateral switches
HEF4066B
gates
Notes
1. Vis is the input voltage at a Y or Z terminal, whichever is assigned as input.
2. Vos is the output voltage at a Y or Z terminal, whichever is assigned as output.
3. RL =10k to VSS; CL = 50 pF to VSS; En =VDD;Vis =VDD (square-wave); see Figs 6 and 10.
4. RL =10k;CL = 50 pF to VSS; En =VDD (square-wave);
Vis =VDD and RL to VSS for tPHZ and tPZH;
Vis =VSS and RL to VDD for tPLZ and tPZL; see Figs 6 and 11.
5. RL =10k; CL = 15 pF; En =VDD; Vis = 12 VDD(p-p) (sine-wave, symmetrical about 12 VDD); fis = 1 kHz; see Fig.7.
6. RL =1k; Vis = 12 VDD(p-p) (sine-wave, symmetrical about 12 VDD);
7. RL =10k to VSS; CL = 15 pF to VSS; En =VDD (square-wave); crosstalk is Vos (peak value); see Fig.6.
8. RL =1k; CL = 5 pF; En =VSS; Vis = 12 VDD(p-p) (sine-wave, symmetrical about 12 VDD);
9. RL =1k; CL = 5 pF; En =VDD; Vis = 12 VDD(p-p) (sine-wave, symmetrical about 12 VDD);
VDD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
800 fi +∑ (foCL) × VDD 2
where
dissipation per
10
3 500 fi +∑ (foCL) × VDD 2
fi = input freq. (MHz)
package (P)
15
10 100 fi +∑ (foCL) × VDD 2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (f
oCL) = sum of outputs
VDD = supply voltage (V)
20 log
V
os (B)
V
is A
()
-------------------
-50 dB; E
n (A)
V
SS E
;
n B
()
V
DD ; see Fig. 8.
==
=
20 log
V
os
V
is
---------
-50 dB; see Fig. 7.
=
20 log
V
os
V
is
---------
-3 dB; see Fig. 7.
=
Fig.6
Fig.7
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