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參數(shù)資料
| 型號(hào)： | 935260792112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | ADC |
| 英文描述： | 3-CH 6-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | PLASTIC, SOT-340-1, SSOP-24 |
| 文件頁(yè)數(shù)： | 23/24頁(yè) |
| 文件大?。?/td> | 206K |
| 代理商： | 935260792112 |
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1996 Jul 30
8
Philips Semiconductors
Product specication
6-bit analog-to-digital converter
with multiplexer and clamp
TDA8706A
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
2. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB
× 6.02 + 1.76 dB.
3. Output data acquisition: the output data is available after the maximum delay time of td.
Timing (fclk = 40 MHz; CL = 20 pF); Tamb =25 °C; see Fig.3
OUTPUT DATA; note 3
tds
sampling delay time
7ns
th
output hold time
5
ns
td
output delay time
VDDO = 4.75 V
12
15
ns
VDDO = 3.15 V
17
20
ns
VDDO = 2.70 V
18
21
ns
SELECT INPUT SIGNALS SR, SG, SB AND CLP
tsu
set-up time SR, SG and SB
with no overlap; see Fig.3
10
ns
with overlap
see Fig.4
ns
tr
rise time SR, SG and SB
10% to 90%
4
6
ns
tf
fall time SR, SG and SB
90% to 10%
4
6
ns
tover
R, G and B (active) overlap
time with respect to select
signals SR, SG and SB
see Fig.4
0
ns
tCLPP
clamp pulse time
CCLP =10nF
3
s
tMH
multiplexer hold time
SR, SG and SB
9
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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