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參數(shù)資料
| 型號(hào)： | 935260803112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 偏轉(zhuǎn) |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP32 |
| 封裝： | PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 10/63頁 |
| 文件大小： | 318K |
| 代理商： | 935260803112 |
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1999 Jul 13
18
Philips Semiconductors
Product specication
I2C-bus autosync deection controllers for
PC/TV monitors
TDA4853; TDA4854
Horizontal oscillator: pins HCAP and HREF
ffr(H)
free-running frequency without
PLL1 action (for testing only)
RHBUF = ∞;
RHREF = 2.4 k;
CHCAP = 10 nF; note 3
30.53
31.45
32.39
kHz
f
fr(H)
spread of free-running
frequency (excluding spread of
external components)
±3.0
%
TCfr
temperature coefcient of
free-running frequency
100
0
+100
106/K
fH(max)
maximum oscillator frequency
130
kHz
VHREF
voltage at input for reference
current
2.43
2.55
2.68
V
Unlock blanking detection: pin HUNLOCK
Vscan(HUNLOCK)
low level voltage of HUNLOCK
saturation voltage in case
of locked PLL1; internal
sink current = 1 mA
250
mV
Vblank(HUNLOCK)
blanking level of HUNLOCK
external load current = 0
0.9
1
1.1
V
TCblank
temperature coefcient of
Vblank(HUNLOCK)
0.9
mV/K
TCsink
temperature coefcient of
Isink(HUNLOCK)
0.15
%/K
Isink(int)
internal sink current
for blanking pulses;
PLL1 locked
1.4
2.0
2.6
mA
IL(max)
maximum external load current
VHUNLOCK =1V
2mA
IL
leakage current
VHUNLOCK = 5 V in case of
unlocked PLL1 and/or
protection active
±5
A
PLL1 phase comparator and frequency-locked loop: pins HPLL1 and HBUF
tW(HSYNC)(max)
maximum width of horizontal
sync pulse (referenced to line
period)
25
%
tlock(HPLL1)
total lock-in time of PLL1
40
80
ms
Ictrl(HPLL1)
control currents
notes 4 and 5
locked mode, level 1
15
A
locked mode, level 2
145
A
VHBUF
buffered f/v voltage at HBUF
(pin 27)
minimum horizontal
frequency
2.5
V
maximum horizontal
frequency
0.5
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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