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參數資料
| 型號： | 935260845112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, SOT-369-1, SSOP-16 |
| 文件頁數： | 18/18頁 |
| 文件大?。?/td> | 172K |
| 代理商： | 935260845112 |
1998 Nov 19
9
Philips Semiconductors
Product specication
Low-voltage frequency synthesizer for
radio telephones
UMA1021AM
SERIAL BUS TIMING CHARACTERISTICS
VDD1 =VDD2 =VCC =3V; Tamb =25 °C; unless otherwise specied.
Note
1. The minimum pulse width (tW) can be smaller than 4000 ns when the both conditions are fulfilled:
a) Main divider input frequency:
b) Reference divider input frequency:
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Serial programming clock; CLK
tr
rise time
10
40
ns
tf
fall time
10
40
ns
Tcy
clock cycle time
100
ns
Enable programming; E
tSTART
delay to rising clock edge
40
ns
tEND
delay from last falling clock edge
20
ns
tW
minimum inactive pulse width
note 1
4000
ns
tSU;E
enable set-up time to next clock edge
20
ns
Register serial input data; DATA
tSU;DAT
input data to clock set-up time
20
ns
tHD;DAT
input data to clock hold time
20
ns
f
RF
447
t
W
----------
>
f
xtal
3
t
W
------
>
Fig.3 Serial bus timing diagram.
handbook, full pagewidth
MBG368
MSB
LSB
ADDRESS
tSTART
tSU;DAT
tHD;DAT
Tcy
tr
tf
tW
tEND tSU;E
CLK
DATA
E
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