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參數(shù)資料
| 型號： | 935261120112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SOT-341-1, SSOP-28 |
| 文件頁數(shù)： | 2/29頁 |
| 文件大?。?/td> | 241K |
| 代理商： | 935261120112 |
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1999 Jan 06
10
Philips Semiconductors
Product specication
10-bit high-speed low-power ADC
TDA8763A
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 1023:
a) Voffset(B) (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00
and the reference voltage BOTTOM (VRB) at Tamb =25 °C.
b) Voffset(T) (voltage offset TOP) is the difference between reference voltage TOP (VRT) and the analog input which
produces data outputs equal to code 1023 at Tamb =25 °C.
TWO-TONE; note 8
TTIR
two-tone intermodulation
rejection
fclk = 40 MHz
69
dB
BIT ERROR RATE
BER
bit error rate
fclk = 50 MHz;
fi = 4.43 MHz;
VI = ±16 LSB at code 512
1013
times/
sample
DIFFERENTIAL GAIN; note 9
Gdiff
differential gain
fclk = 40 MHz;
PAL modulated ramp
0.8
%
DIFFERENTIAL PHASE; note 9
diff
differential phase
fclk = 40 MHz;
PAL modulated ramp
0.4
deg
Timing (fclk = 40 MHz; CL = 15 pF); see Fig.4; note 10
tds
sampling delay time
3
ns
th
output hold time
4
ns
td
output delay time
VCCO = 4.75 V
10
13
ns
VCCO = 3.15 V
12
15
ns
CL
digital output load capacitance
15
pF
3-state output delay times; see Fig.5
tdZH
enable HIGH
5.5
8.5
ns
tdZL
enable LOW
12
15
ns
tdHZ
disable HIGH
19
24
ns
tdLZ
disable LOW
12
15
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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