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參數(shù)資料
| 型號(hào)： | 935261242118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 20-BIT DAC, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, SSOP-16 |
| 文件頁(yè)數(shù)： | 20/21頁(yè) |
| 文件大小： | 142K |
| 代理商： | 935261242118 |
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2000 Jan 10
8
Philips Semiconductors
Preliminary specication
Low-cost stereo lter DAC
UDA1320ATS
9
L3 INTERFACE DESCRIPTION
9.1
The L3 interface
The following system and digital sound processing
features can be controlled in the microcontroller mode of
the UDA1320ATS/N2:
System clock frequency
Data input format
De-emphasis for 32 kHz, 44.1 kHz and 48 kHz
Volume
Soft mute.
The exchange of data and control information between the
microcontroller and the UDA1320ATS/N2 is accomplished
through a serial hardware interface comprising the
following pins:
L3DATA
L3MODE
L3CLOCK.
Information transfer through the microcontroller bus is
organized in accordance with the L3 format, in which two
different modes of operation can be distinguished; address
mode and data transfer mode (see Figs 4 and 6).
The address mode is required to select a device
communicating via the L3 bus and to define the
destination registers for the data transfer mode.
Data transfer can only be in one direction, consisting of
input to the UDA1320ATS/N2 to program sound
processing and other functional features.
Data bits 7 to 2 represent a 6-bit device address, bit 7
being the MSB. The address of the UDA1320ATS/N2 is
000101 (bit 7 to bit 2). If the UDA1320ATS/N2 receives a
different address, it will deselect its microcontroller
interface logic.
9.2
Data transfer mode
The selected address remains active during subsequent
data transfers until the UDA1320ATS/N2 receives a new
address command. The fundamental timing of data
transfers is essentially the same as in the address mode,
see Fig.6. The maximum input clock and data rate is 64 fs.
All transfers are by 8-bit bytes. Data will be stored in the
UDA1320ATS/N2 after reception of a complete byte. See
Fig.5 for a multi-byte transfer.
Table 4
Selection of data transfer
BIT 1
BIT 0
TRANSFER
0
DATA (volume, de-emphasis, mute)
0
1
not used
1
0
STATUS (system clock frequency,
data input format)
1
not used
Fig.4 Timing address mode.
handbook, full pagewidth
t h(L3)A
t h(L3)DA
t su(L3)DA
Tcy(CLK)(L3)
BIT 0
L3MODE
L3CLCK
L3DATA
BIT 7
MBK072
tCLK(L3)H
tCLK(L3)L
t su(L3)A
t h(L3)A
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