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參數(shù)資料
| 型號(hào)： | 935261329518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| 封裝： | PLASTIC, SOT-401-1, LQFP-32 |
| 文件頁(yè)數(shù)： | 20/22頁(yè) |
| 文件大小： | 147K |
| 代理商： | 935261329518 |
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1999 Oct 06
7
Philips Semiconductors
Preliminary specication
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
Track enable input (pin TEN); see Table 2
VIL
LOW-level input voltage
0
0.8
V
VIH
HIGH-level input voltage
2
VCCD
V
IIL
LOW-level input current
VTEN =0
5
A
IIH
HIGH-level input current
VTEN =VCCD
5
A
Inputs (pins INP and INN); analog input voltage referenced to AGND; VREFIN = 1.27 V; see Table 3
Vi(p-p)
input voltage range
(peak-to-peak value)
Vi =VINP VINN;
Tamb =25 °C
0.90
0.97
1.040
V
T
CI
input voltage range drift
0.5
mV/K
Vi(os)
input offset voltage
output code = 127
25
+25
mV
Zi
input impedance
fINP = 50 MHz
90
k
Ci
input capacitance
fINP = 50 MHz
2
pF
IIL
LOW-level input current
VINP =VREFOUT + 0.5
1
A
VINP =VREFOUT 0.5
1
A
IIH
HIGH-level input current
VINP =VREFOUT + 0.5
40
A
VINP =VREFOUT 0.5
40
A
Adjustable full scale range; VREFIN = 1.2 to 1.35 V; see Fig.3
VI(p-p)
input voltage range
(peak-to-peak value)
Vi =VINP VINN;
Tamb =25 °C
1
V
Voltage controlled regulator input pin VREFIN (referenced to AGND); note 3
Vi(ref)
reference voltage
tbf
1.25
tbf
V
Ii(ref)
input current on pin VREFIN
tbf
1.1
mA
Outputs; ADC data outputs
VOL
LOW-level output voltage
IO =1mA
0.5
V
VOH
HIGH-level output voltage
IO = 0.4 mA
VCCO 0.5
VCCO
V
CL
output load capacitance
10
pF
δv/δt
slew rate
10% to 90%; CL =10pF
1.2
V/ns
Switching characteristics; note 2; see Table 1
fCLK(min)
minimum clock frequency
track = LOW
6
MHz
fCLK(max)
maximum clock frequency
100
MHz
tW(CLKH)
clock pulse width HIGH
4
ns
tW(CLKL)
clock pulse width LOW
4
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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