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參數資料
| 型號： | 935261329551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| 封裝： | PLASTIC, SOT-401-1, LQFP-32 |
| 文件頁數： | 21/22頁 |
| 文件大?。?/td> | 147K |
| 代理商： | 935261329551 |
1999 Oct 06
8
Philips Semiconductors
Preliminary specication
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
TDA8793
Analog signal processing; note 3; see Figs 4, 5, 6 and 7
INL
integral non-linearity
ramp input; fCLK = 2 MHz;
VCCA =VCCD =3V
±0.8
tbf
LSB
DNL
differential non-linearity
ramp input; fCLK = 2 MHz;
VCCA =VCCD =3V
±0.25
tbf
LSB
S/N
signal-to-noise ratio (full scale)
without harmonics;
fCLK = 100 MHz
fi = 20 MHz
42
45
dB
fi = 50 MHz
45
dB
BW(3dB)
3 dB analog bandwidth
350
MHz
THD
total harmonics distortion
fi = 20 MHz
56
dB
fi = 50 MHz
52
dB
Hfund(FS)
full scale fundamental harmonics
fCLK = 100 MHz
fi = 20 MHz
0dB
fi = 50 MHz
0dB
HD2(FS)
second harmonic distortion (full
scale) all components included
differential inputs;
fCLK = 100 MHz
fi = 20 MHz
66
dB
fi = 50 MHz
57
dB
single-ended input;
fCLK = 100 MHz
fi = 20 MHz
66
dB
fi = 50 MHz
55
dB
HD3(FS)
third harmonic distortion (full scale)
all components included
differential inputs;
fCLK = 100 MHz
fi = 20 MHz
64
dB
fi = 50 MHz
61
dB
single-ended input;
fCLK = 100 MHz
fi = 20 MHz
64
dB
fi = 50 MHz
59
dB
SFDR
spurious free dynamic range
fCLK = 100 MHz
dB
fi = 20 MHz
57
dB
fi = 50 MHz
54
dB
EB
effective bits
fCLK = 100 MHz; note 4
bits
fi = 20 MHz
7.0
7.4
bits
fi = 50 MHz
7.2
bits
Data timing; fCLK = 100 MHz; CL =10pF; see Fig.8
tds
sampling delay
1.5
ns
th
output hold time
3
ns
td
output delay time
58ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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