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參數資料
| 型號： | 935262254557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | PLASTIC, SOT-317-2, QFP-64 |
| 文件頁數： | 17/40頁 |
| 文件大小： | 250K |
| 代理商： | 935262254557 |
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1999 Feb 24
24
Philips Semiconductors
Product specication
Triple high-speed Analog-to-Digital
Converter (ADC)
TDA8752A
GFINE
ne gain correction range
ne register input code = 0;
(see Fig.9)
0
dB
ne register input
code = 31; (see Fig.9)
0.5
dB
Gamp/T
amplier gain stability as a
function of temperature
Vref = 2.5 V with
100 ppm/
°C maximum
variation
200
ppm/
°C
IGC
gain current
±20
A
tstab
amplier gain adjustment
speed
HSYNC active; capacitors
on pins 8, 16 and 24 = 22 nF
25
mdB/
s
Vi(p-p)
input voltage range
(peak-to-peak value)
corresponding to full-scale
output
0.4
1.2
V
tr(Vi)
input voltage rise time
fi = 100 MHz; square wave
2.5
ns
tf(Vi)
input voltage fall time
fi = 100 MHz; square wave
2.5
ns
GE(rms)
channel-to-channel gain
matching (RMS value)
maximum coarse gain;
Tamb =25 °C
1
%
minimum coarse gain;
Tamb =25 °C
2
%
Clamps
PCLP
precision
black level noise on RGB
channels = 10 mV (max.)
(RMS value); Tamb =25 °C
1
+1
LSB
tCOR1
clamp correction time to within
±10 mV
±100 mV black level input
variation; clamp
capacitor = 4.7 nF
300
ns
tCOR2
clamp correction time to less
than 1 LSB
±100 mV black level input
variation; clamp
capacitor = 4.7 nF
10
lines
tW(CLP)
clamp pulse width
500
2000
ns
CLPE
channel-to-channel clamp
matching
1
+1
LSB
Aoff
code clamp reference
clamp register input
code = 0
63.5
LSB
clamp register input
code = 255
64
LSB
Phase-locked loop
jPLL(rms)
long term PLL jitter
(RMS value)
fCLK = 60 MHz; see Table 13
450
ps
fCLK = 100 MHz;
see Table 13
360
ps
DR
divider ratio
100
4095
fref
reference clock frequency
range
15
280
kHz
fPLL
output clock frequency range
12
100
MHz
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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