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參數資料
| 型號： | 935262321518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 4/43頁 |
| 文件大?。?/td> | 193K |
| 代理商： | 935262321518 |
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1999 May 31
12
Philips Semiconductors
Product specication
Digital video encoder
SAA7126H; SAA7127H
I2C-bus format
Table 4
I2C-bus address; see Table 5
Table 5
Explanation of Table 4
Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.
2. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.
Slave receiver
Table 6
Subaddresses 26H and 27H
Table 7
Subaddress 28H
S
SLAVE ADDRESS
ACK
SUBADDRESS
ACK
DATA 0
ACK
--------
DATA n
ACK
P
PART
DESCRIPTION
S
START condition
Slave address
1000100X or 1 0 0 0 1 1 0 X; note 1
ACK
acknowledge, generated by the slave
Subaddress; note 2
subaddress byte
DATA
data byte
--------
continued data bytes and ACKs
P
STOP condition
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
WSS
wide screen signalling bits
3 to 0 = aspect ratio
7 to 4 = enhanced services
10 to 8 = subtitles
13 to 11 = reserved
WSSON
0
wide screen signalling output is disabled; default after reset
1
wide screen signalling output is enabled
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
REMARKS
BS
starting point of burst in clock cycles
PAL: BS = 33 (21H); default after reset
NTSC: BS = 25 (19H)
DECCOL
0
disable colour detection bit of RTCI input
1
enable colour detection bit of RTCI input
bit RTCE must be set to logic 1 (see Fig.13)
DECFIS
0
eld sequence as FISE in subaddress 61
1
eld sequence as FISE bit in RTCI input
bit RTCE must be set to logic 1 (see Fig.13)
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