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參數資料
| 型號： | 935262601518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, SOT-307, QFP-44 |
| 文件頁數： | 27/59頁 |
| 文件大小： | 232K |
| 代理商： | 935262601518 |
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2000 Mar 08
33
Philips Semiconductors
Product specication
Digital video encoder
SAA7128H; SAA7129H
Table 61 Subaddress 71H
Table 62 Subaddress 72H
Table 63 Subaddress 73H
Table 64 Subaddress 74H
Table 65 Subaddress 75H
BIT
SYMBOL
DESCRIPTION
7 to 0
RCV2E[7:0]
These are the 8 LSBs of the 11-bit code that determines the end of the output signal
on the RCV2 pin; the 3 MSBs of the 11-bit code are held at subaddress 72H (see
Table 62). Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed. Leading
sync slope at CVBS output coincides with trailing slope of RCV2 out at RCV2E = 49H.
BIT
SYMBOL
DESCRIPTION
7
This bit is reserved and must be set to a logic 0.
6
RCV2E10
These are the 3 MSBs of end of output signal code; see Table 61.
5
RCV2E9
4
RCV2E8
3
This bit is reserved and must be set to a logic 0.
2
RCV2S10
These are the 3 MSBs of start of output signal code; see Table 60.
1
RCV2S9
0
RCV2S8
BIT
SYMBOL
DESCRIPTION
7 to 0
TTXHS[7:0]
Start of signal on pin TTXRQ; see Fig.23.
PAL: TTXHS[7:0] = 42H
NTSC: TTXHS[7:0] = 54H
BIT
SYMBOL
DESCRIPTION
7 to 0
TTXHD[7:0]
Indicates the delay in clock cycles between rising edge of TTXRQ output and valid
data at pin TTX.
minimum value: TTXHD[7:0] = 2
BIT
SYMBOL
DESCRIPTION
7
CSYNCA4
Advanced composite sync against RGB output from 0 to 31 LLC clock periods.
6
CSYNCA3
5
CSYNCA2
4
CSYNCA1
3
CSYNCA0
2
VS_S2
Vertical sync shift between RCV1 and RCV2 (switched to output); in master mode it is
possible to shift Hsync (RCV2; CBLF = 0) against Vsync (RCV1; SRCV1 = 00)
standard value: VS_S[2:0] = 3.
1
VS_S1
0
VS_S0
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