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參數資料
| 型號： | 935262838551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數： | 23/23頁 |
| 文件大小： | 183K |
| 代理商： | 935262838551 |
1998 Aug 26
9
Philips Semiconductors
Preliminary specication
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8768
THERMAL NOISE
Nth(rms)
thermal noise (RMS value)
grounded input;
fCLK = 40 MHz
0.25
tbf
LSB
SPURIOUS FREE DYNAMIC RANGE
DRsf
spurious free dynamic range
fi = 4.43 MHz
tbf
69
dB
fi = 10 MHz
tbf
dB
fi = 20 MHz
tbf
dB
SIGNAL-TO-NOISE RATIO; note 5
S/N
signal-to-noise ratio
without harmonics;
fCLK = 40 MHz; fi = 4.43 MHz
67
dB
EFFECTIVE NUMBER OF BITS; note 5
Nbit
effective number of bits
TDA8768H/4 (fCLK = 40 MHz)
fi = 4.43 MHz
10.3
bits
fi =10MHz
tbf
bits
fi =15MHz
tbf
bits
effective number of bits
TDA8768H/5 (fCLK = 55 MHz)
fi = 4.43 MHz
9.9
bits
fi =10MHz
tbf
bits
fi =15MHz
tbf
bits
fi =20MHz
tbf
bits
INTERMODULATION; note 6
TTIR
two-tone intermodulation
rejection
fCLK = 40 MHz
tbf
66
dB
d3
third order intermodulation
distortion
fCLK = 40 MHz
tbf
67
dB
BIT ERROR RATE
BER
bit error rate
fCLK = 40 MHz;
fi = 4.43 MHz;
VI = ±16 LSB at code 2047
1015
tbf
times/
sample
Timing (CL = 10 pF); see Fig.3 and note 7
td(s)
sampling delay time
2ns
th
output hold time
4
ns
td
output delay time
VCCO = 5.25 V
10
15
ns
VCCO = 3.0 V
13
18
ns
3-state output delay times; see Fig.4
tdZH
enable HIGH
14
18
ns
tdZL
enable LOW
16
20
ns
tdHZ
disable HIGH
16
20
ns
tdLZ
disable LOW
14
18
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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