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參數資料
| 型號： | 935263898112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SOT-341-1, SSOP-28 |
| 文件頁數： | 28/29頁 |
| 文件大小： | 186K |
| 代理商： | 935263898112 |
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2000 Jul 03
8
Philips Semiconductors
Product specication
10-bit high-speed low-power ADC
TDA8764A
Reference voltages for the resistor ladder; see Table 1
VRB
reference voltage BOTTOM
1.2
1.3
2.2
V
VRT
reference voltage TOP
3.4
3.7
VCCA 0.8
V
Vdiff(ref)
differential reference voltage
VRT VRB
2.2
2.4
3.2
V
Iref
reference current
Vdiff = 2.4 V
17.6
mA
RLAD
resistor ladder
136
TCRLAD
temperature coefcient of the
resistor ladder
1860
ppm
253
m
/K
Voffset(B)
offset voltage BOTTOM
Vdiff = 2.4 V; note 3
200
mV
Voffset(T)
offset voltage TOP
Vdiff = 2.4 V; note 3
190
mV
VI(p-p)
analog input voltage
(peak-to-peak value)
Vdiff = 2.4 V; note 4
1.95
2.01
2.10
V
Outputs
PINS D9 TO D0 AND IR (REFERENCED TO OGND)
VOL
LOW-level output voltage
IOL = 1 mA
0
0.5
V
VOH
HIGH-level output voltage
IOH = 1mA
VCCO 0.5
VCCO
V
IOZ
output current in 3-state mode
0.5 V < VO <VCCO
20
+20
A
Switching characteristics
PIN CLK; see Fig.5; note 1
fclk(max)
maximum clock frequency
60
MHz
tCPH
clock pulse width HIGH
Tamb =25 °C
7.0
ns
tCPL
clock pulse width LOW
Tamb =25 °C
3.5
ns
Analog signal processing
LINEARITY
INL
integral non-linearity
fclk = 60 MHz; ramp input
±0.8
±2
LSB
DNL
differential non-linearity
fclk = 60 MHz; ramp input;
no missing code
±0.35 ±0.9
LSB
Eoffset
offset error
middle code
±1
LSB
EG
gain error (from device to device) note 5
±0.5
%
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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