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參數資料
| 型號： | 935271530118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013, SOT-137-1, SO-24 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 329K |
| 代理商： | 935271530118 |
PCK351
1:10 clock distribution device with 3-State outputs
Rev. 01 — 14 May 2002
Product data
1.
Description
The PCK351 is a high-performance 3.3 V LVTTL clock distribution device. The
PCK351 enables a single clock input to be distributed to ten outputs with minimum
output skew and pulse skew. The use of distributed VCC and GND pins in the PCK351
ensures reduced switching noise.
The PCK351 is characterized for operation over the supply range 3.0 V to 3.6 V, and
over the industrial temperature range
40 to +85 °C.
2.
Features
s 1:10 LVTTL clock distribution
s Low output to output skew
s Low output pulse skew
s Over voltage tolerant inputs and outputs
s LVTTL-compatible inputs and outputs
s Distributed VCC and ground pins reduce switching noise
s Balanced High-drive outputs (
32 mA I
OH, 32 mA IOL)
s Reduced power dissipation due to the state-of-the-art QuBICLP process
s Supply range of +3.0 V to +3.6 V
s Package options include plastic small-outline (D) and shrink small-outline (DB)
packages
s Industrial temperature range
40 to +85 °C
s PCK351 is identical to and replaces PTN3151.
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